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101 innovation drive san jose, ca 95134 www.altera.com sv5v3-1.8 11.1 volume 1: overview and datasheet stratix v device handbook
? 2012 altera corporation. all rights reserved. altera, arria, cy clone, hardcopy, max, megacore , nios, quartus and stratix word s and logos are trademarks of alte ra corporation and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specificat ions in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no respon sibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet iso 9001:2008 registered
february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet contents chapter revision dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v chapter 1. stratix v device family overview stratix v family variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 stratix v features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?3 stratix v family plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?4 low-power serial transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?10 pcie gen3, gen2, and gen1 hard ip (embedded hardcopy block) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?12 external memory and gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?13 adaptive logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?13 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 fractional pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 embedded memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?14 variable precision dsp block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?15 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 incremental compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?16 enhanced configuration and cvp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 partial reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?17 automatic single event upset error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?1 8 hardcopy v devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?18 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?19 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1?20 chapter 2. dc and switching charac teristics for stratix v devices electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?5 internal weak pull-up resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?10 i/o standard specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?11 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?14 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 transceiver performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?15 core performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 clock tree specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 pll specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?21 dsp block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?23 memory block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?24 jtag configuration specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?25 temperature sensing diode specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 periphery performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 high-speed i/o specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?26 dll range, dqs logic block, and memory output cloc k jitter specifications . . . . . . . . . . . . . 2?31 oct calibration block specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?33 duty cycle distortion (dcd) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?33 i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?34 programmable ioe delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?34
iv contents stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet programmable output buffer delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?34 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?35 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2?38 additional information how to contact altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1 typographic conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . info?1
february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet chapter revision dates the chapters in this document, stratix v device handbook volume 1 , were revised on the following dates. where chapters or groups of chapters are available separately, part numbers are listed. chapter 1. stratix v device family overview revised: february 2012 part number: sv51001-2.3 chapter 2. dc and switching characteristics for stratix v devices revised: february 2012 part number: sv53001-2.3
vi chapter revision dates stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet
sv51001-2.3 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix v device handbook volume 1: overview and datasheet february 2012 subscribe iso 9001:2008 registered 1. stratix v device family overview this chapter provides an overview of the stratix ? v devices and their features. many of these devices and features are enabled in the quartus ? ii software version 11.1. the remaining devices and features will be enabled in future versions of the quartus ii software. f to find out more about the upcoming stra tix v devices and features, refer to the stratix v upcoming device features document. altera?s 28-nm stratix v fpgas include i nnovations such as an enhanced core architecture, integrated transceivers up to 28.05 gigabits per second (gbps), and a unique array of integrated hard intellectual property (ip) blocks. with these innovations, stratix v fpgas deliver a new class of application-targeted devices optimized for: bandwidth-centric applications and protocols, including pci express ? (pcie ? ) gen3 data-intensive applications for 40g/100g and beyond high-performance, high-precision digital signal processing (dsp) applications stratix v devices are available in four variants (gt, gx, gs, and e), each targeted for a different set of applications. for higher volume production, you can prototype with stratix v fpgas and use the low-risk, low-cost path to hardcopy ? v asics. stratix v family variants stratix v gt devices, with both 28.05-gbps and 12.5-gbps transceivers, are optimized for applications that require ultra-high bandwidth and performance in areas such as 40g/100g/400g optical co mmunications systems and optical test systems. 28.05-gbps and 12.5-gbps transc eivers are also known as gt and gx channels, respectively. stratix v gx devices offer up to 66 integrated 14.1-gbps transceivers supporting backplanes and optical modules. these de vices are optimized for high-performance, high-bandwidth applications such as 40g/100g optical transport, packet processing, and traffic management found in wireline , military communications, and network test equipment markets. stratix v gs devices have an abundance of variab le precision dsp blocks, supporting up to 3,926 18x18 or 1,963 27x27 multipliers. in addition, stratix v gs devices offer integrated 14.1-gbps transceivers, which support backplanes an d optical modules. these devices are optimized for transceiver- based dsp-centric applications found in wireline, military, broadcast, and high-performance computing markets. february 2012 sv51001-2.3
1?2 chapter 1: stratix v device family overview stratix v family variants stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet stratix v e devices offer the highest logic density within the stratix v family with nearly one million logic elements (les) in the largest device. these devices are optimized for applications such as asic an d system emulation, diagnostic imaging, and instrumentation. common to all stratix v family variants are a rich set of high-performance building blocks, including a redesigned adaptive logic module (alm), 20 kbit (m20k) embedded memory blocks, variable pr ecision dsp blocks, and fractional phase-locked loops (plls). all of these building bl ocks are interconnected by altera?s superior multi-track routing architecture and comprehensive fabric clocking network. also common to stratix v devices is the new embedded hardcopy block, which is a customizable hard ip block that leverages altera?s unique hardcopy asic capabilities. the embedded ha rdcopy block in stratix v fpgas is used to harden ip instantiation of pcie gen3, gen2, and gen1.
chapter 1: stratix v device family overview 1?3 stratix v features summary february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet stratix v features summary technology 28-nm tsmc process technology 0.85-v core voltage low-power serial transceivers 28.05-gbps transceivers on stratix v gt devices electronic dispersion compensation (edc) for xfp, sfp+, qsfp, cfp optical module support adaptive linear and decision feedback equalization 600-megabits per second (mbps) to 14.1-gbps backplane capability transmit pre-emphasis and de-emphasis dynamic reconfiguration of individual channels on-chip instrumentation (eyeq non-intrusive data eye monitoring) general-purpose i/os (gpios) 1.4-gbps lvds 1,066-mhz external memory interface on-chip termination (oct) 1.2-v to 3.3-v interfacing for all stratix v devices embedded hardcopy block pcie gen3, gen2, and gen1 complete protocol stack, x1/x2/x4/x8 end point and root port embedded transceiver hard ip interlaken physical coding sublayer (pcs) gigabit ethernet (gbe) and xaui pcs 10g ethernet pcs serial rapidio ? (srio) pcs common public radio interface (cpri) pcs gigabit passive optical networking (gpon) pcs power management programmable power technology quartus ii integrated powerplay power analysis high-performance core fabric enhanced alm with four registers improved routing architecture reduces congestion and improves compile times embedded memory blocks m20k: 20-kbit with hard error correction code (ecc) mlab: 640-bit variable precision dsp blocks up to 500 mhz performance natively support signal processing with precision ranging from 9x9 up to 54x54 new native 27x27 multiply mode 64-bit accumulator and cascade for systolic finite impulse responses (firs) embedded internal coefficient memory pre-adder/subtractor improves efficiency increased number of outputs allows more independent multipliers fractional plls fractional mode with third-order delta-sigma modulation integer mode precision clock synthesis, clock delay compensation, and zero delay buffer (zdb) clock networks 717-mhz fabric clocking global, quadrant, and peripheral clock networks unused clock networks can be powered down to reduce dynamic power device configuration serial and parallel flash interface enhanced advanced encryption standard (aes) design security features tamper protection partial and dynamic reconfiguration configuration via protocol (cvp) high-performance packaging multiple device densities with identical package footprints enables seamless migration between different fpga densities fbga packaging with on-package decoupling capacitors lead and rohs-compliant lead-free options hardcopy v migration
1?4 chapter 1: stratix v device family overview stratix v family plan stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet stratix v family plan table 1?1 lists the stratix v gt device features. table 1?1. stratix v gt device features feature 5sgtc5 5sgtc7 logic elements (k) 425 622 registers (k) 642 939 28.05/12.5-gbps transceivers 4/32 4/32 pcie hard ip blocks 1 1 fractional plls 28 28 m20k memory blocks 2,304 2,560 m20k memory (mbits) 45 50 variable precision multipliers (18x18) 512 512 variable precision multipliers (27x27) 256 256 ddr3 sdram x72 dimm interfaces 4 4 user i/os, full-duplex lvds, 28.05/12.5-gbps transceivers package (1) , (2), (3) 5sgtc5 5sgtc7 kf40-f1517 (4) 600, 150, 36 600, 150, 36 notes to table 1?1 : (1) packages are flipchip ball grid array (1.0-mm pitch). (2) each package ro w offers pin migration (common board f ootprint) for all devices in the row. (3) for full package details, refer to package information datasheet for altera devices . (4) migration between select stratix v gt devices and stratix v gx devices is availa ble. for more info rmation, refer to table 1?5 on page 1?9 .
chapter 1: stratix v device family overview 1?5 stratix v family plan february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 1?2 lists the stratix v gx device features. table 1?2. stratix v gx device features (part 1 of 2) features 5sgxa3 5sgxa4 5sgxa5 5sgxa7 5sgxa9 5sgxab 5sgxb5 5sgxb6 5sgxb9 5sgxbb logic elements (k) 340 420 490 622 840 952 490 597 840 952 registers (k) 513 634 740 939 1,268 1,437 740 902 1,268 1,437 14.1-gbps transceivers 12, 24, or 36 24 or 36 24, 36, or 48 24, 36, or 48 36 or 48 36 or 48 66 66 66 66 pcie hard ip blocks 1 or 2 1 or 2 1, 2, or 4 1, 2, or 4 1, 2, or 4 1, 2, or 4 1 or 4 1 or 4 1 or 4 1 or 4 fractional plls 20 (1) 24 28 28 28 28 24 24 32 32 m20k memory blocks 957 1,900 2,304 2,560 2,640 2,640 2,100 2,660 2,640 2,640 m20k memory (mbits) 19 37 45 50 52 52 41 52 52 52 variable precision multipliers (18x18) 512 512 512 512 704 704 798 798 704 704 variable precision multipliers (27x27) 256 256 256 256 352 352 399 399 352 352 ddr3 sdram x72 dimm interfaces 4466 6 6 4444 user i/os, full-duplex lvds, 14.1-gbps transceivers package (2) , (3) , (4) , (5) 5sgxa3 5sgxa4 5sgxa5 5sgxa7 5sgxa9 5sgxab 5sgxb5 5sgxb6 5sgxb9 5sgxbb eh29-h780 360, 90, 12 h ??? ? ? ???? hf35-f1152 (6) 432, 108, 24 552, 138, 24 552, 138, 24 552, 138, 24 ? ? ? ? ? ? kf35-f1152 432, 108, 36 432, 108, 36 432, 108, 36 432, 108, 36 ? ? ? ? ? ? kf40-f1517 / kh40-h1517 (6) 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 h 696, 174, 36 h ???? nf40-f1517 (7) ? ? 600, 150, 48 600, 150, 48 ? ? ? ? ? ? rf40-f1517 ? ? ? ? ? ? 432, 108, 66 432, 108, 66 ? ? rf43-f1760 ? ? ? ? ? ? 600, 150, 66 600, 150, 66 ? ? rh43-h1760 ? ? ? ? ? ? ? ? 600, 150, 66 h 600, 150, 66 h nf45-f1932 (6) ? ? 840, 210, 48 840, 210, 48 840, 210, 48 840, 210, 48 ? ? ? ?
1?6 chapter 1: stratix v device family overview stratix v family plan stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet notes to table 1?2 : (1) the f1517 package contains 24 plls. the othe r packages with this d evice contain 20 plls. (2) packages are flipchip ball grid array (1.0-mm pitch). (3) lvds counts are full duplex channels. ea ch full duplex channe l is one transmitter (tx) pair plus one receiver (rx) pair. (4) each package row offers pin migration (common circuit bo ard footprint) for all devices in the row. (5) h indicates that this device is only available in a hybrid p ackage. hybrid packages are slight ly larger than conventional fbgas. refer to altera?s packaging docu mentation for more information. (6) migration between select stratix v gx devices and stratix v gs devices is avail able. for more information, refer to table 1?5 on page 1?9 . (7) migration between select stratix v gx devices and stratix v gt d evices is available. for more information, refer to table 1?5 on page 1?9 . table 1?2. stratix v gx device features (part 2 of 2) features 5sgxa3 5sgxa4 5sgxa5 5sgxa7 5sgxa9 5sgxab 5sgxb5 5sgxb6 5sgxb9 5sgxbb
chapter 1: stratix v device family overview 1?7 stratix v family plan february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 1?3 lists the stratix v gs device features. table 1?3. stratix v gs device features features 5sgsd3 5sgsd4 5sgsd5 5sgsd6 5sgsd8 logic elements (k) 236 360 457 583 695 registers (k) 356 543 690 880 1,050 14.1-gbps transceivers 12 or 24 12, 24, or 36 24 or 36 36 or 48 36 or 48 pcie hard ip blocks 1 1 1 1, 2, or 4 1, 2, or 4 fractional plls 20 20 (1) 24 28 28 m20k memory blocks 688 957 2,014 2,320 2,567 m20k memory (mbits) 13 19 39 45 50 variable precision multipliers (18x18) 1,200 2,088 3,180 3,550 3,926 variable precision multipliers (27x27) 600 1,044 1,590 1,775 1,963 ddr3 sdram x72 dimm interfaces 2 4 4 6 6 user i/os, full-duplex lvds, 14.1-gbps transceivers package (2) , (3) , (4) , (5) 5sgsd3 5sgsd4 5sgsd5 5sgsd6 5sgsd8 eh29-h780 360, 90, 12 h 360, 90, 12 h ??? hf35-f1152 (6) 432, 108, 24 432, 108, 24 552, 138, 24 ? ? kf40-f1517 (6) ? 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 nf45-f1932 (6) ? ? ? 840, 210, 48 840, 210, 48 notes to table 1?3 : (1) the f1517 package contains 24 plls. the othe r packages with this device contain 20 plls. (2) packages are flipchip ball grid array (1.0-mm pitch). (3) lvds counts are full duplex chan nels. each full duplex channel is one tx pair plus one rx pair. (4) each package row offers pin migration (common circ uit board footprint) for all devices in the row. (5) h indicates that this device is only availabl e in a hybrid package. hybrid packages are slightly larger than conventional fbgas. refer to altera?s packaging documentation for more information. (6) migration between select stra tix v gs devices and stratix v gx devices is available. for more in formation, refer to table 1?5 on page 1?9 .
1?8 chapter 1: stratix v device family overview stratix v family plan stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet table 1?4 lists the stratix v e device features. table 1?4. stratix v e device features features 5see9 5seeb logic elements (k) 840 952 registers (k) 1,268 1,437 fractional plls 28 28 m20k memory blocks 2,640 2,640 m20k memory (mbits) 52 52 variable precision multipliers (18x18) 704 704 variable precision multipliers (27x27) 352 352 ddr3 sdram x72 dimm interfaces 6 6 user i/os, full-duplex lvds package (1) , (2) , (3), (4) 5see9 5seeb h40-h1517 696, 174 h 696, 174 h f45-f1932 840, 210 840, 210 notes to table 1?4 : (1) packages are flipchip ball grid array (1.0-mm pitch). (2) lvds counts are full duplex chan nels. each full duplex channel is one tx pair plus one rx pair. (3) each package row offers pin migration (common circuit boar d footprint) for all devices in the row. (4) h indicates that this device is only available in a hybrid package. hybr id packages are slightly larger than conventional fbgas. refer to altera?s pa ckaging documentation fo r more information.
chapter 1: stratix v device family overview 1?9 stratix v family plan february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet each row in table 1?5 lists which devices allow migration. table 1?5. device migration list across all stratix v device variants (1) package stratix v gx stratix v gt stratix v gs stratix v e a3 a4 a5 a7 a9 ab b5 b6 b9 bb c5 c7 d3 d4 d5 d6 d8 e9 eb eh29-h780 v v v hf35-f1152 (2) vvvv vvv kf35-f1152 v v v v kf40-f1517 / kh40-h1517 vvvvvv vvvv nf40 / kf40-f1517 (3) v v v v rf40-f1517 vv h40-h1517 v v rf43-f1760 vv nf45-f1932 v v v v v v f45-f1932 vv rh43-h1760 v v notes to table 1?5 : (1) all devices in a given row allow migration. (2) all devices in this row are in the hf35 package and have twen ty-four 14.1-gbps transceivers. (3) the 5sgtc5/7 devices in the kf40 pack age have four 28.05-gbps transceivers and thir ty-two 12.5-gbps transceivers. other devi ces in this row are in the nf40 pa ckage and have fort y-eight 14.1-gbps transceivers.
1?10 chapter 1: stratix v device family overview low-power serial transceivers stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet low-power serial transceivers stratix v fpgas deliver the industry?s most flexible transceivers with the highest bandwidth from 600 mbps to 28.05 gbps, low bit error ratio (ber), and low power. stratix v transceivers have many enhancemen ts to improve flexibility and robustness. these enhancements include robust analog receive clock and data recovery (cdr), advanced pre-emphasis, and eq ualization. in addition, all transceivers are identical with the full featured embedded pcs hard ip to simplify the design, lower the power, and save valuable core resources. stratix v transceivers are comp liant with a wide range of standard protocols and data rates and are equipped with a variety of signal-conditioning features to support backplane, optical module, and chip-to-chip applications. stratix v transceivers are loca ted on the left and right sides of the device, as shown in figure 1?1 . the transceivers are isolated from the rest of the chip to prevent core and i/o noise from coupling into the transceivers, thereby ensuring optimal signal integrity. the transceiver channels consist of the physical medium attachment (pma), pcs, and high-speed clock networks. you can also use the unused transceiver pma channels as additional transmit plls. table 1?6 lists the transceiver pma features. figure 1?1. stratix v gt, gx, and gs device chip view (1) notes to figure 1?1 : (1) this figure represents a given variant of a stratix v device with transceivers. other variants ma y have a different floorpla n than the one shown here. (2) you can use the unused tran sceiver channels as additional transceiver transmit plls. pcs pcs pcs pcs pcs pma pma pma pma pma (2) clock networks m20k blocks dsp blocks m20k blocks dsp blocks m20k blocks dsp blocks core logic fabric core logic fabric pma per channel: standard pcs, 10g pcs pma per channel: standard pcs, 10g pcs embedded hardcopy block embedded hardcopy block embedded hardcopy block embedded hardcopy block i/o, lvds, and memory interface i/o, lvds, and memory interface fractional plls fractional plls
chapter 1: stratix v device family overview 1?11 low-power serial transceivers february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 1?6 lists the pma features for the stratix v transceivers. the stratix v core logic connects to the pcs th rough an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or 66-bit interface, depending on the transceiver data rate and protocol. stratix v devices contain pcs hard ip to support pcie gen3, gen2, gen1, interlaken, 10ge, xaui, gbe, srio, cpri, and gpon protocols. all othe r standard and proprietary protocols are supported through the transceiver pcs hard ip. table 1?7 lists the transceiver pcs features. table 1?6. transceiver pma features feature capability backplane support 10gbase-r, 14.1 gbps (stratix v gx and gs devices), 12.5 gbps (stratix v gt devices) cable driving support pcie cable and esata applications optical module support with edc 10g form-factor pluggable (xfp), small form-factor pluggable (sfp+), quad small form-factor pluggable (qsfp), cxp, 100g pluggable (cfp), 100g form-factor pluggable chip-to-chip support 28.05 gbps and 12.5 gbps (stratix v gt devices) and 14.1 gbps (stratix v gx and gs devices) continuous time linear equalization (ctle) receiver 4-stage linear equalization to support high-attenuation channels decision feedback equalization (dfe) receiver 5-tap digital equalizer to minimize losses and crosstalk adaptive equalization (aeq) adaptive engine to automatically adjust equalization to compensate for changes over time pll-based clock recovery superior jitter tolerance versus phase interpolation techniques programmable deserialization and word alignment flexible deserialization width and configurable word alignment patterns transmit equalization (pre-emphasis) transmit driver 4-tap pre-emphasis and de-emphasis for protocol compliance under lossy conditions ring and logic cell oscillator transmit plls choice of transmit plls per channel, optimized for specific protocols and applications on-chip instrumentation (eyeq data-eye monitor) allows non-intrusive on-chip monitoring of both width and height of the data eye dynamic reconfiguration allows reconfiguration of single channels without affecting operation of other channels protocol support compliance with over 50 industry standard protocols in the range of 600 mbps to 28 gbps table 1?7. transceiver pcs features (part 1 of 2) protocol data rates (gbps) transmit data path receiver data path custom phy 0.6 to 8.5 phase compensation fifo, byte serializer, 8b/10b encoder, bit-slip, and channel bonding word aligner, de-skew fifo, rate match fifo, 8b/10b decoder, byte deserializer, and byte ordering custom 10g phy 9.98 to 14.1 tx fifo, gear box, and bit-slip rx fifo and gear box x1, x4, x8 pcie gen1 and gen2 2.5 and 5.0 same as custom phy plus pipe 2.0 interface to core logic same as custom phy plus pipe 2.0 interface to core logic
1?12 chapter 1: stratix v device family overview pcie gen3, gen2, and gen1 hard ip (embedded hardcopy block) stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet pcie gen3, gen2, and gen1 hard ip (embedded hardcopy block) stratix v devices have pcie hard ip designed for performance, ease-of-use, and increased functionality. the pcie hard ip consists of the pcs, data link, and transaction layers. the pcie hard ip supports gen3, gen2, and gen1 end point and root port up to x8 lane configurations. the stratix v pcie hard ip operates independently from the core logic, which allows the pcie link to wake up and complete li nk training in less than 100 ms while the stratix v device completes loading the programming file for the rest of the fpga. the pcie hard ip also provides added functionality, which helps you support emerging features such as single root i/o virtua lization (sr-iov) or optional protocol extensions. in addition, the stratix v device pcie hard ip has improved end-to-end data path protection using ecc and enables device cvp. in all stratix v devices, the primary pcie ha rd ip that supports cvp is always in the bottom left corner of the device (iobank_b0l) when viewing the die from the top. x1, x4, x8 pcie gen3 8 phase compensation fifo, encoder, scrambler, gear box, and bit slip block synchronization, rate match fifo, decoder, de-scrambler, and phase compensation fifo 10g ethernet 10.3125 tx fifo, 64/66 encoder, scrambler, and gear box rx fifo, 64/66 decoder, de-scrambler, block synchronization, and gear box interlaken 4.9 to 10.3125 tx fifo, frame generator, crc-32 generator, scrambler, disparity generator, and gear box rx fifo, frame generator, crc-32 checker, frame decoder, descrambler, disparity checker, block synchronization, and gearbox 40gbase-r ethernet 4 x 10.3125 tx fifo, 64/66 encoder, scrambler, alignment marker insertion, gearbox, and block striper rx fifo, 64/66 decoder, de-scrambler, lane reorder, deskew, alignment marker lock, block synchronization, gear box, and destripper 100gbase-r ethernet 10 x 10.3125 otn 40 and 100 (4 +1) x 11.3 tx fifo, channel bonding, and byte serializer rx fifo, lane deskew, and byte de-serializer (10 +1) x 11.3 gbe 1.25 same as custom phy plus gbe state machine same as custom phy plus gbe state machine xaui 3.125 to 4.25 same as custom phy plus xaui state machine for bonding four channels same as custom phy plus xaui state machine for re-aligning four channels srio 1.25 to 6.25 same as custom phy plus srio v2.1 compliant x2 and x4 channel bonding same as custom phy plus srio v2.1-compliant x2 and x4 deskew state machine cpri 0.6144 to 9.83 same as custom phy plus tx deterministic latency same as custom phy plus rx deterministic latency gpon 1.25, 2.5, and 10 same as custom phy same as custom phy table 1?7. transceiver pcs features (part 2 of 2) protocol data rates (gbps) transmit data path receiver data path
chapter 1: stratix v device family overview 1?13 external memory and gpio february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet external memory and gpio each stratix v i/o block has a hard fifo th at improves the resynchronization margin as data is transferred from memory to the fpga. the hard fifo also lowers phy latency, resulting in higher random a ccess performance. gpios include on-chip dynamic termination to reduce the number of external components and minimize reflections. on-package decoupling capacitors suppress noise on the power lines, which reduce noise coupling into the i/os. memory banks are isolated to prevent core noise from coupling to the output, thus re ducing jitter and providing optimal signal integrity. the external memory interface block uses advanced calibration algorithms to compensate for process, voltage and temper ature (pvt) variations in the fpga and external memory components. the ad vanced algorithms ensure maximum bandwidth and a robust timing margin across all conditions. stratix v devices deliver a complete memory solution with the high performance memory controller ii (hpmc ii) and uniphy megacore ? ip that simplifies a design for today?s advanced memory modules. table 1?8 lists external memory interface block performance. adaptive logic module stratix v devices use an improved alm to im plement logic functions more efficiently. the stratix v alm has eight inputs with a fracturable look-up table (lut), two dedicated embedded adders, and four dedicated registers. the stratix v alm has the following enhancements: table 1?8. external memory interface performance (1) interface performance (mhz) ddr3 1,066 ddr2 533 qdr ii 350 qdr ii+ 550 rldram ii 533 rldram iii 800 note to table 1?8 : (1) the specifications listed in this table are performance targets. fo r a current achievable performance, use the external memory interface spec estimator .
1?14 chapter 1: stratix v device family overview clocking stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet clocking the stratix v device core clock network is designed to support 717-mhz fabric operations and 1,066-mhz and 1,600-mbps external memory interfaces. the clock network architecture is based on altera?s proven global, quad rant, and peripheral clock structure, which is supported by dedi cated clock input pins and fractional clock synthesis plls. the quartus ii software identifies all unused sections of the clock network and powers them down, which reduces power consumption. fractional pll stratix v devices have up to 28 fractional plls that you can use to reduce both the number of oscillators required on the board and the clock pins used in the fpga by synthesizing multiple clock frequencies fr om a single reference clock source. in addition, you can use the fractional plls for clock network delay compensation, zero delay buffering, and transmit clocking for transceivers. fractional plls may be individually configured for integer mode or fractional mode with third-order delta-sigma modulation. embedded memory stratix v devices contain two types of em bedded memory blocks: mlab (640-bit) and m20k (20-kbit). mlab blocks are ideal fo r wide and shallow me mories. m20k blocks are useful for supporting larger memory configurations and include ecc. both types operate up to 600 mhz and can be configured to be a single- or dual-port ram, fifo, rom, or shift register. these memory blocks are flexible and support a number of memory configuratio ns, as shown in table 1?9 . the quartus ii software simplifies design re-use by automatically mapping memory blocks from legacy stratix devices in to the stratix v memory architecture. table 1?9. embedded memory block configuration mlab (640 bits) m20k (20,480 bits) 32x20 64x10 512x40 1kx20 2kx10 4kx5 8kx2 16kx1
chapter 1: stratix v device family overview 1?15 variable precision dsp block february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet variable precision dsp block stratix v fpgas feature the industry?s first variable precision dsp block that you can configure to natively support signal proce ssing with precision ranging from 9x9 to 36x36. you can independently configure each dsp bl ock at compile time as either a dual 18x18 multiply accumulate or a single 27x27 multiply accumulate. with a dedicated 64-bit cascade bus, you can cascade multiple variable precision dsp blocks to implement even higher precision dsp functions efficiently. table 1?10 lists how variable precision is accommodated within a dsp block or by using multiple blocks. complex multiplication is common in ds p algorithms. one of the most popular applications of complex multipliers is th e fast fourier transform (fft) algorithm, which increases precision requirements on only one side of the multiplier. the variable precision dsp block is designed to support the fft algorithm with a proportional increase in dsp resources with precision growth. table 1?11 lists complex multiplication with variable precision dsp blocks. for fft applications with high dynamic range requirements, only the altera ? fft megacore offers an option of single precis ion floating point implementation, with the resource usage and performance simi lar to high-precision fixed point implementations. other new features include: table 1?10. variable precision dsp block configurations multiplier size (bits) dsp block resources expected usage 9x9 1/3 of variable precision dsp block low precision fixed point 18x18 1/2 of variable precision dsp block medium precision fixed point 27x27 1 variable precision dsp block high precision fixed or single precision floating point 36x36 2 variable precision dsp blocks very high precision fixed point table 1?11. complex multiplication with variable precision dsp blocks multiplier size (bits) dsp block resources expected usage 18x18 2 variable precision dsp blocks resource optimized ffts 18x25 3 variable precision dsp blocks accommodate bit growth through fft stages 18x36 4 variable precision dsp blocks highest precision fft stages 27x27 4 variable precision dsp blocks single precision floating point
1?16 chapter 1: stratix v device family overview power management stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet the variable precision dsp block is ideal for higher bit precision in high-performance dsp applications. at the same time, the variable precision dsp block can efficiently support the many existing 18-bit dsp appl ications, such as high definition video processing and remote radio heads. stratix v fpgas, with the variable precision dsp block architecture, are the only fpga family that can efficiently support many different precision levels, up to and including floating point implementations. this flexibility results in increased system performance, reduced power consumption, and reduced architecture constraints for system algorithm designers. power management stratix v devices leverage fpga architectural features and process technology advancements to reduce total power consumption by up to 30% when compared with stratix iv devices at the same performance level. stratix v devices continue to provide programmable power technology, introduced in earlier generations of stratix fpga families. the quartus ii software powerplay feature identifies critical timing paths in a de sign and biases core logic in that path for high performance. powerplay also identifies non-critical timing paths and biases core logic in that path for low power instead of high performance. powerplay automatically biases core logic to meet performance and optimize power consumption. additionally, stratix v devices have a number of hard ip blocks that reduce logic resources and deliver substantial power savings when compared with soft implementations. the list includes pcie gen1/gen2/gen3, interlaken pcs, hard i/o fifos, and transceivers. hard ip blocks consume up to 50% less power than equivalent soft implementations. stratix v transceivers are designed for power efficiency. the transceiver channels consume 50% less power than stratix iv fpgas. the transceiver pma consumes approximately 90 mw at 6.5 gbps and 170 mw at 12.5 gbps. incremental compilation the quartus ii software incremental compilat ion feature reduces compilation time by up to 70% and preserves performance to ease timing closure. incremental compilation supports top-down, bottom-up, and team -based design flows. incremental compilation facilitates modular hierarchic al and team-based design flows where a team of designers work in parallel on a design. different designers or ip providers can develop and optimize different blocks of the design independently, which you can then import into the top-level project.
chapter 1: stratix v device family overview 1?17 enhanced configuration and cvp february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet enhanced configuration and cvp stratix v device configuration is enhanced for ease-of-use, speed, and cost. stratix v devices support a new 4-bit bus active seri al mode (asx4). asx4 supports up to a 400-mbps data rate using small low-cost quad interface flash devices. asx4 mode is easy to use and offers an ideal balance between cost and speed. finally, the fast passive parallel (fpp) interface is enhanced to support 8-, 16-, and 32-bit data widths to meet a wide range of performance and cost goals. you can configure stratix v fpgas using cv p with pcie. cvp with pcie divides the configuration process into two parts: the pcie hard ip and periphery and the core logic fabric. cvp uses a much smaller amou nt of external memory (flash or rom) because cvp has to store only the configur ation file for the pcie hard ip and periphery. the 100-ms power-up to active ti me (for pcie) is much easier to achieve when only the pcie hard ip and peripher y are loaded. after the pcie hard ip and periphery are loaded and the root port is booted up, application software running on the root port can send the configuration file for the fpga fabric across the pcie link where the file is loaded into the fpga. the fpga is then fully configured and functional. table 1?12 lists the configuration modes available for stratix v devices. partial reconfiguration partial reconfiguration allows you to reconfigure part of the fpga while other sections continue to operate. this capability is required in systems where uptime is critical because partial reconfiguration allows you to make updates or adjust functionality without disrupting services. while lowering power and cost, partial reconfiguration also increases the effective logic density by removing the necessity to place the fpga functions that do not oper ate simultaneously. instead, you can store these functions in external memory and lo ad them as required. this capability reduces the size of the fpga by allowing multiple applications on a single fpga, saving board space and reducing power. you no longer need to know all the details of the fpga architecture to perform partial reconfiguration. altera simplifies the proc ess by extending the power of incremental compilation used in earlier versions of the quartus ii software. table 1?12. configuration modes for stratix v devices mode fast or slow por compression encryption remote update data width max clock rate (mhz) max data rate (mbps) active serial (as) vvvv 1, 4 100 400 passive serial (ps) vvv ? 1 125 125 fast passive parallel (fpp) vvv (1) 8, 16, 32 125 3,000 cvp ? ? vv 1, 2, 4, 8 ? 3,000 partial reconfiguration ?? vv 16 125 2,000 jtag ? ? ? ? 1 33 33 note to table 1?12 : (1) remote update support with the parallel flash loader.
1?18 chapter 1: stratix v device family overview automatic single event upset error detection and correction stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet partial reconfiguration is supported in the following configurations: automatic single event upset error detection and correction stratix v devices offer single event upset (seu) error detection and correction circuitry that is robust and easy to use. th e correction circuitry includes protection for configuration ram (cram) programming bi ts and user memories. the cram is protected by a continuously running cyclical redundancy check (crc) error detection circuit with integrated ecc that automati cally corrects one or double-adjacent bit errors and detects higher order multi-bit errors. when more than two errors occur, correction is available through a core programming file reload that refreshes a design while the fpga is operating. the physical layout of the fpga is optimized to make the majority of multi-bit upsets appear as independent single - or double-adjacent bit errors, which are automatically corrected by the integrated cram ecc circui try. in addition to the cram protection in stratix v devices, user memories in clude integrated ecc circuitry and are layout-optimized to enable error detection of 3-bit errors and correction for 2-bit errors. hardcopy v devices hardcopy v asics offer the lowest risk and lowest total cost in asic designs with embedded high-speed transceivers. you can prototype and debug with stratix v fpgas, then use hardcopy v asics for volume production. the proven turnkey process creates a functionally equivalent hardcopy v asic with or without embedded transceivers to meet all timing constraints in as little as 12 weeks. the powerful combination of stratix v fpgas and hardcopy v asics can help you meet your design requirements. whether yo u plan for asic production and require the lowest-risk, lowest-cost path from spec ification to production or require a cost reduction path for your fpga-based system s, altera provides the optimal solution for power, performance, and device bandwidth.
chapter 1: stratix v device family overview 1?19 ordering information february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet ordering information this section describes ordering informatio n for stratix v gt, gx, gs, and e devices. figure 1?2 shows the ordering codes for stratix v devices. figure 1?2. ordering information for stratix v devices note to figure 1?2 : (1) you can select one or bo th of these options, or yo u can ignore these options. family signature embedded hardcopy block variant transceiver count transceiver pma speed grade package type ball array dimension corresponds to pin count operating temperature transceiver pcs and fpga fabric speed grade optional suffix (1) gx : 14.1-gbps transceivers gt : 28.05-gbps transceivers gs: dsp-oriented e: highest logic density, no transceivers m : mainstream e : extended 5s : stratix v gx gt gs e a3 c5 d3 e9 a4 c7 d4 eb a5 d5 a7 d6 a9 d8 ab b5 b6 b9 bb e : 12 h : 24 k : 36 n : 48 r : 66 1 (fastest) 2 3 f : fineline bga h : hybrid fineline bga 29 : 780 pins 35 : 1,152 pins 40 : 1,517 pins 43 : 1,760 pins 45 : 1,932 pins c : commercial (0-85 c) i : industrial (?40-100 c) 1 (fastest) 2 3 4 n : lead-free packaging es : engineering sample silicon 5s gx m a5 k 3 f 35 c 2 n es member code family variant
1?20 chapter 1: stratix v device family overview revision history stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet revision history table 1?13 lists the revision history for this chapter. table 1?13. revision history (part 1 of 2) date version changes made february 2012 2.3 updated table 1?2 , table 1?3, table 1?4 , and table 1?5 . updated figure 1?2 . updated ?automatic single event upset error detection and correction? on page 1?18 . minor text edits. december 2011 2.2 updated table 1?2 and table 1?3. november 2011 2.1 changed stratix v gt transceiver speed from 28 gbps to 28.05 gbps. updated figure 1?2. november 2011 2.0 revised figure 1?2. updated table 1?5. minor text edits. september 2011 1.10 updated table 1?2, table 1?3, and table 1?4. september 2011 1.9 updated table 1?1, table 1?2, table 1?3, table 1?4, and table 1?5. updated figure 1?2. minor text edits. june 2011 1.8 changed 800 mhz to 1,066 mhz for ddr3 in table 1?8 and in text. may 2011 1.7 for stratix v gt devices, changed 14.1 gbps to 12.5 gbps. changed configuration via pcie to configuration via protocol updated table 1?1, table 1?2, table 1?3, table 1?4, table 1?5, and table 1?6. chapter moved to volume 1. january 2011 1.6 added stratix v gs information. updated tables listing device features. added device migration information. updated 12.5-gbps transceivers to 14.1-gbps transceivers december 2010 1.5 updated table 1-1. december 2010 1.4 updated table 1-1. updated figure 1-2. converted to the new template. minor text edits. july 2010 1.3 updated table 1?5
chapter 1: stratix v device family overview 1?21 revision history february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet july 2010 1.2 updated ? features summary? on page 1?2 updated resource counts in table 1?1 and table 1?2 removed ?interlaken pcs hard ip? and ?10g ethernet hard ip? added ?40g and 100g ethernet hard ip (embedded hardcopy block)? on page 1?7 added information about configuration via pcie added ?partial reconfiguration? on page 1?12 added ?ordering information? on page 1?14 may 2010 1.1 updated part numbers in table 1?1 and table 1?2 april 2010 1.0 initial release table 1?13. revision history (part 2 of 2) date version changes made
1?22 chapter 1: stratix v device family overview revision history stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet
sv53001-2.3 ? 2012 altera corporation. all rights reserved. altera, arria, cyclone, hardcopy, max, megaco re, nios, quartus and stratix word s and logos are trademarks of altera corporat ion and registered in the u.s. patent and trademark office and in other countries. all other w ords and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accordance wi th altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability ar ising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customer s are advised to obtain the latest version of device specificat ions before relying on any published information and before placing orders for products or services. stratix v device handbook volume 1: overview and datasheet february 2012 subscribe iso 9001:2008 registered 2. dc and switching characteristics for stratix v devices this chapter covers the electrical an d switching characteristics for stratix ? v devices. electrical characteristics include operating conditions and power consumption. switching characteristics include transceiver specifications, core, and periphery performance. this chapter also describe s i/o timing, including programmable i/o element (ioe) delay and progra mmable output buffer delay. f for information regarding the densities and packages of devices in the stratix v family, refer to the stratix v device family overview chapter. electrical characteristics the following sections describe the electrical characteristics of stratix v devices. operating conditions when you use stratix v devices, they ar e rated according to a set of defined parameters. to maintain the highest possible performance and reliability of stratix v devices, you must consider the operating requirements described in this chapter. stratix v devices are offered in commercial and industrial grades. commercial devices are offered in ?1 (fastest), ?2, ?3, and ?4 sp eed grades. industrial devices are offered in ?3 and ?4 speed grades. absolute maximum ratings absolute maximum ratings define the maxi mum operating conditions for stratix v devices. the values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. the functional operation of the device is not implied for these conditions. c conditions other than those listed in table 2?1 may cause permanent damage to the device. additionally, device operation at the absolute maximum ratings for extended periods of time may have ad verse effects on the device. table 2?1. absolute maximum ratings for stratix v devices?preliminary (part 1 of 2) symbol description minimum maximum unit v cc power supply for core voltage and periphery circuitry ?0.5 1.35 v v ccpt power supply for programmable power technology ?0.5 1.8 v v ccpgm power supply for configuration pins ?0.5 3.75 v v cc_aux auxiliary supply for the programmable power technology ?0.5 3.75 v february 2012 sv53001-2.3
2?2 chapter 2: dc and switching characteristics for stratix v devices electrical characteristics stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet table 2?2 lists the absolute conditions for the transceiver power supply for stratix v gx, gs, and gt devices. v ccbat battery back-up power supply for design security volatile key register ?0.5 3.75 v v ccpd i/o pre-driver power supply ?0.5 3.75 v v ccio i/o power supply ?0.5 3.9 v v ccd_fpll pll digital power supply ?0.5 3.75 v v cca_fpll pll analog power supply ?0.5 3.75 v v i dc input voltage ?0.5 4.0 v i out dc output current per pin ?25 40 ma t j operating junction temperature ?55 125 c t stg storage temperature (no bias) ?65 150 c table 2?1. absolute maximum ratings for stratix v devices?preliminary (part 2 of 2) symbol description minimum maximum unit table 2?2. transceiver power supply absolute conditions for stratix v gx, gs, and gt devices symbol description devices minimum maximum unit v cca_gxbl transceiver channel pll power supply (left side) gx, gs, gt ?0.5 3.75 v v cca_gxbr transceiver channel pll power supply (right side) gx, gs ?0.5 3.75 v v cca_gtbr transceiver channel pll power supply (right side) gt ?0.5 3.75 v v cchip_l transceiver hard ip power supply (left side) gx, gs, gt ?0.5 1.35 v v cchip_r transceiver hard ip power supply (right side) gx, gs, gt ?0.5 1.35 v v cchssi_l transceiver pcs power supply (left side) gx, gs, gt ?0.5 1.35 v v cchssi_r transceiver pcs power supply (right side) gx, gs, gt ?0.5 1.35 v v ccr_gxbl receiver analog power supply (left side) gx, gs, gt ?0.5 1.35 v v ccr_gxbr receiver analog power supply (right side) gx, gs, gt ?0.5 1.35 v v ccr_gtbr receiver analog power supply for gt channels (right side) gt ?0.5 1.35 v v cct_gxbl transmitter analog power supply (left side) gx, gs, gt ?0.5 1.35 v v cct_gxbr transmitter analog power supply (right side) gx, gs, gt ?0.5 1.35 v v cct_gtbr transmitter analog power supply for gt channels (right side) gt ?0.5 1.35 v v ccl_gtbr transmitter clock network power supply (right side) gt ?0.5 1.35 v v cch_gxbl transmitter output buffer power supply (left side) gx, gs, gt ?0.5 1.8 v v cch_gxbr transmitter output buffer power supply (right side) gx, gs, gt ?0.5 1.8 v
chapter 2: dc and switching characteristics for stratix v devices 2?3 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet maximum allowed overshoot and undershoot voltage during transitions, input signals may overshoot to the voltage shown in table 2?3 and undershoot to ?2.0 v for input currents less than 100 ma and periods shorter than 20 ns. table 2?3 lists the maximum allowed input oversh oot voltage and the duration of the overshoot voltage as a percentage of device lifetime. the maximum allowed overshoot duration is specified as a percenta ge of high time over the lifetime of the device. a dc signal is equivalent to 100% of the duty cycle. for example, a signal that overshoots to 3.95 v can be at 3.95 v for only ~5% over the lifetime of the device; for a device lifetime of 10 years, the over shoot duration amounts to half a year. table 2?3. maximum allowed overshoot during transitions?preliminary symbol description condition (v) overshoot duration as % @ t j = 100c unit vi (ac) ac input voltage 3.8 100 % 3.85 64 % 3.9 36 % 3.95 21 % 412% 4.05 7 % 4.1 4 % 4.15 2 % 4.2 1 %
chapter 2: dc and switching characteristics for stratix v devices 2?4 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet recommended operating conditions this section lists the functional operating limits for the ac and dc parameters for stratix v devices. table 2?4 lists the steady-state voltag e and current values expected from stratix v devices. power supply ramps must all be strictly monotonic, without plateaus. table 2?4. recommended operating conditions for stratix v devices?preliminary symbol description condition minimum typical maximum unit v cc core voltage and periphery circuitry power supply ? 0.820.850.88v v ccpt power supply for programmable power technology ? 1.451.501.55v v cc_aux auxiliary supply for the programmable power technology ? 2.375 2.5 2.625 v v ccpd (1) i/o pre-driver (3.0 v) power supply ? 2.85 3.0 3.15 v i/o pre-driver (2.5 v) power supply ? 2.375 2.5 2.625 v v ccio i/o buffers (3.0 v) power supply ? 2.85 3.0 3.15 v i/o buffers (2.5 v) power supply ? 2.375 2.5 2.625 v i/o buffers (1.8 v) power supply ? 1.71 1.8 1.89 v i/o buffers (1.5 v) power supply ? 1.425 1.5 1.575 v i/o buffers (1.35 v) power supply ? 1.283 1.35 1.45 v i/o buffers (1.25 v) power supply ? 1.19 1.25 1.31 v i/o buffers (1.2 v) power supply ? 1.14 1.2 1.26 v v ccpgm configuration pins (3.0 v) power supply ? 2.85 3.0 3.15 v configuration pins (2.5 v) power supply ? 2.375 2.5 2.625 v configuration pins (1.8 v) power supply ? 1.71 1.8 1.89 v v cca_fpll pll analog voltage regulator power supply ? 2.375 2.5 2.625 v v ccd_fpll pll digital voltage regulator power supply ? 1.45 1.5 1.55 v v ccbat (2) battery back-up power supply (for design security volatile key register) ? 1.2?3.0v v i dc input voltage ? ?0.5 ? 3.6 v v o output voltage ? 0 ? v ccio v t j operating junction temperature commercial 0 ? 85 c industrial ?40 ? 100 c t ramp power supply ramp time standard por 200 s ? 100 ms ? fast por 200 s ? 4 ms ? notes to table 2?4 : (1) v ccpd must be 2.5 v when v ccio is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 v. v ccpd must be 3.0 v when v ccio is 3.0 v. (2) if you do not use the design security feature in stratix v devices, connect v ccbat to a 2.5- or 3.0-v power supply. stratix v power-on-reset (por) circuitry monitors v ccbat . stratix v devices will not exit por if v ccbat stays at logic low.
chapter 2: dc and switching characteristics for stratix v devices 2?5 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 2?5 lists the transceiver power supply recommended operating conditions for stratix v gx, gs, and gt devices. dc characteristics this section lists the supply current, i/o pin leakage current, input pin capacitance, on-chip termination tolerance, and hot socketing specifications. supply current standby current is the current drawn from the respective power rails used for power budgeting. use the excel-based early powe r estimator (epe) to get supply current estimates for your design because these currents vary greatly with the resources you use. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook. table 2?5. recommended transceiver power supply operating conditions for stratix v gx, gs, and gt devices symbol description devices minimum typical maximum unit v cca_gxbl (1) transceiver channel pll power supply (left side) gx, gs, gt 2.85, 2.375 3.0, 2.5 3.15, 2.625 v v cca_gxbr (1) transceiver channel pll power supply (right side) gx, gs 2.85, 2.375 3.0, 2.5 3.15, 2.625 v v cca_gtbr transceiver channel pll power supply (right side) gt 2.85 3.0 3.15 v v cchip_l transceiver hard ip power supply (left side) gx, gs, gt 0.82 0.85 0.88 v v cchip_r transceiver hard ip power supply (r ight side) gx, gs, gt 0.82 0.85 0.88 v v cchssi_l transceiver pcs power supply (left side) gx, gs, gt 0.82 0.85 0.88 v v cchssi_r transceiver pcs power supply (right side) gx, gs, gt 0.82 0.85 0.88 v v ccr_gxbl (2) receiver analog power supply (left side) gx, gs, gt 0.82, 0.95 0.85, 1.0 0.88, 1.05 v v ccr_gxbr (2) receiver analog power supply (right side) gx, gs, gt 0.82, 0.95 0.85, 1.0 0.88, 1.05 v v ccr_gtbr receiver analog power supply for gt channels (right side) gt 0.95 1.0 1.05 v v cct_gxbl (2) transmitter analog power supply (left side) g x, gs, gt 0.82, 0.95 0.85, 1.0 0.88, 1.05 v v cct_gxbr (2) transmitter analog power supply (right side) g x, gs, gt 0.82, 0.95 0.85, 1.0 0.88, 1.05 v v cct_gtbr transmitter analog power supply for gt channels (right side) gt 0.95 1.0 1.05 v v ccl_gtbr transmitter clock network power supply gt 0.95 1.0 1.05 v v cch_gxbl transmitter output buffer power supply (left side) gx, gs, gt 1.425 1.5 1.575 v v cch_gxbr transmitter output buffer power supply (right side) gx, gs, gt 1.425 1.5 1.575 v notes to table 2?5 : (1) this supply must be connected to 3.0 v if the cmu pll, receiver cdr, or both, are c onfigured at a base data rate > 6.5 gbps. up to 6.5 gbps, you can connect this supply to either 3.0 v or 2.5 v. (2) this supply must be connected to 1.0 v if the transceiver is configured at a data rate > 6.5 gbps. up to 6.5 gbps, you can con nect this supply to either 1.0 v or 0.85 v.
2?6 chapter 2: dc and switching characteristics for stratix v devices electrical characteristics stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet i/o pin leakage current table 2?6 lists the stratix v i/o pin leakage current specifications. bus hold specifications table 2?7 lists the stratix v device family bus hold specifications. on-chip termination (oct) specifications if you enable oct calibration, calibration is automatically performed at power-up for i/os connected to the calibration block. table 2?8 lists the stratix v oct termination calibration accuracy specifications. table 2?6. i/o pin leakage current for stratix v devices?preliminary symbol description conditions min typ max unit i i input pin v i = 0 v to v cciomax ?30 ? 30 a i oz tri-stated i/o pin v o = 0 v to v cciomax ?30 ? 30 a table 2?7. bus hold parameters for stratix v devices?preliminary parameter symbol conditions v ccio unit 1.2 v 1.5 v 1.8 v 2.5 v 3.0 v min max min max min max min max min max low sustaining current i susl v in > v il (maximum) 22.5 ? 25.0 ? 30.0 ? 50.0 ? 70.0 ? a high sustaining current i sush v in < v ih (minimum) ?22.5 ? ?25.0 ? ?30.0 ? ?50.0 ? ?70.0 ? a low overdrive current i odl 0v < v in < v ccio ? 120 ? 160 ? 200 ? 300 ? 500 a high overdrive current i odh 0v < v in < v ccio ? ?120 ? ?160 ? ?200 ? ?300 ? ?500 a bus-hold trip point v trip ? 0.450.950.501.000.681.070.701.700.802.00 v table 2?8. oct calibration accuracy specifications for stratix v devices?preliminary (1) (part 1 of 2) symbol description conditions calibration accuracy unit c2 c3,i3 c4,i4 25- ? r s internal series termination with calibration (25- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 15 15 15 % 50- ? r s internal series termination with calibration (50- ? setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 15 15 15 %
chapter 2: dc and switching characteristics for stratix v devices 2?7 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet 34- ? and 40- ? r s internal series termination with calibration (34- ? and 40- ? setting) v ccio = 1.5, 1.35, 1.25, 1.2 v 15 15 15 % 48- ????? - ??? and 80- ? r s internal series termination with calibration (48- ??? 60- ??? and 80- ? setting) v ccio = 1.2 v 15 15 15 % 50- ? r t internal parallel termination with calibration (50- ? setting) v ccio = 2.5, 1.8, 1.5, 1.2 v ?10 to +40 ?10 to +40 ?10 to +40 % 20- ? , 30-? , 40- ? ,60- ??? and 120- ? r t internal parallel termination with calibration (20- ? , 30- ??? 40- ??? 60- ??? and 120- ? setting) v ccio = 1.5, 1.35, 1.25 v ?10 to +40 ?10 to +40 ?10 to +40 % 60- ? and 120- ?? r t internal parallel termination with calibration (60- ? and 120- ? setting) v ccio = 1.2 ?10 to +40 ?10 to +40 ?10 to +40 % 25- ? r s_left_shift internal left shift series termination with calibration (25- ? r s_left_shift setting) v ccio = 3.0, 2.5, 1.8, 1.5, 1.2 v 15 15 15 % note to table 2?8 : (1) oct calibration accuracy is valid at the time of calibration only. table 2?8. oct calibration accuracy specifications for stratix v devices?preliminary (1) (part 2 of 2) symbol description conditions calibration accuracy unit c2 c3,i3 c4,i4
chapter 2: dc and switching characteristics for stratix v devices 2?8 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet calibration accuracy for the calibrated series and parallel octs are applicable at the moment of calibration. when process, vo ltage, and temperature (pvt) conditions change after calibration, the tolerance may change. table 2?9 lists the stratix v oct without calibration resistance tolerance to pvt changes. table 2?9. oct without calibration resistance tolerance specifications for stratix v devices?preliminary (1) symbol description conditions resistance tolerance unit c2 c3, i3 c4, i4 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 25- ? r s internal series termination without calibration (25- ? setting) v ccio = 1.2 v 35 50 50 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 3.0 and 2.5 v 30 40 40 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 1.8 and 1.5 v 30 40 40 % 50- ? r s internal series termination without calibration (50- ? setting) v ccio = 1.2 v 35 50 50 % 100- ? r d internal differential termination (100- ? setting) v ccio = 2.5 v 25 25 25 % note to table 2?9 : (1) pending silicon characterization.
chapter 2: dc and switching characteristics for stratix v devices 2?9 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet oct calibration is automatically performed at power-up for oct-enabled i/os. table 2?10 lists the oct variation with temp erature and voltage after power-up calibration. use table 2?10 to determine the oct variation after power-up calibration and equation 2?1 to determine the oct variation without re-calibration. table 2?10 lists the on-chip termination variation after power-up calibration. equation 2?1. oct variation without re-calibration for stratix v devices?preliminary (1) , (2) , (3) , (4) , (5) , (6) notes to equation 2?1 : (1) the r oct value calculated from equation 2?1 shows the range of oct resistance with the variation of temperature and v ccio . (2) r scal is the oct resistance value at power-up. (3) ? t is the variation of temperature with respect to the temperature at power-up. (4) ? v is the variation of voltage with respect to the v ccio at power-up. (5) dr/dt is the percentage change of r scal with temperature. (6) dr/dv is the percentage change of r scal with voltage. table 2?10. oct variation after power-up calibration for stratix v devices?preliminary (1) , (2) symbol description v ccio (v) typical unit dr/dv oct variation with voltage without re-calibration 3.0 0.0297 %/mv 2.5 0.0344 1.8 0.0499 1.5 0.0744 1.2 0.1241 dr/dt oct variation with temperature without re-calibration 3.0 0.189 %/c 2.5 0.208 1.8 0.266 1.5 0.273 1.2 0.317 notes to table 2?10 : (1) valid for a v ccio range of 5% and a temperature range of 0 to 85c. (2) pending silicon characterization. r oct r scal 1 dr dt ------ - ? t ? ?? dr dv ------- ? v ? ?? ? + ?? ?? =
chapter 2: dc and switching characteristics for stratix v devices 2?10 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet pin capacitance table 2?11 lists the stratix v device family pin capacitance. hot socketing table 2?12 lists the hot socketing specifications for stratix v devices. internal weak pull-up resistor table 2?13 lists the weak pull-up resistor values for stratix v devices. table 2?11. pin capacitance for stratix v devices?preliminary symbol description value unit c iotb input capacitance on the top and bottom i/o pins 5.5 pf c iolr input capacitance on the left and right i/o pins 5.5 pf c outfb input capacitance on dual-purpose clock output and feedback pins 5.5 pf table 2?12. hot socketing specifications for stratix v devices?preliminary symbol description maximum i iopin (dc) dc current per i/o pin 300 ? a i iopin (ac) ac current per i/o pin 8 ma (1) i xcvr-tx (dc) (2) dc current per transceiver transmitter pin 100 ma i xcvr-rx (dc) (2) dc current per transceiver receiver pin 50 ma notes to table 2?12 : (1) the i/o ramp rate is 10 ns or more. for ramp rates faster than 10 ns, |i iopin | = c dv/dt, in which c is the i/o pin capacitance and dv/dt is the slew rate. (2) these specifications are preliminary. table 2?13. internal weak pull-up resistor for stratix v devices?preliminary (1) , (2) symbol description v ccio conditions (v) (3) value (4) unit r pu value of the i/o pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option. 3.0 5% 25 k ? 2.5 5% 25 k ? 1.8 5% 25 k ? 1.5 5% 25 k ? 1.35 5% 25 k ? 1.25 5% 25 k ? 1.2 5% 25 k ? notes to table 2?13 : (1) all i/o pins have an opti on to enable the weak pull-up resistor except the configuration, test, and jtag pins. (2) the internal weak pull-down feat ure is only available for the jtag tck pin. the typical value for this internal weak pull-down resistor is approximately 25 k ?? (3) the pin pull-up resistance values may be lower if an external source drives the pin higher than v ccio . (4) these specifications are va lid with a 10% tolerance to cover changes over pvt.
chapter 2: dc and switching characteristics for stratix v devices 2?11 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet i/o standard specifications table 2?14 through table 2?19 list the input voltage (v ih and v il ), output voltage (v oh and v ol ), and current drive characteristics (i oh and i ol ) for various i/o standards supported by stratix v devices. th ese tables also show the stratix v device family i/o standard specifications. the v ol and v oh values are valid at the corresponding i oh and i ol , respectively. for an explanation of the terms used in table 2?14 through table 2?19 , refer to ?glossary? on page 2?35 . table 2?14. single-ended i/o standards for stratix v devices?preliminary i/o standard v ccio (v) v il (v) v ih (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min typ max min max min max max min lvttl 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.4 2.4 2 ?2 lvcmos 2.85 3 3.15 ?0.3 0.8 1.7 3.6 0.2 v ccio ? 0.2 0.1 ?0.1 2.5 v 2.375 2.5 2.625 ?0.3 0.7 1.7 3.6 0.4 2 1 ?1 1.8 v 1.71 1.8 1.89 ?0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.45 v ccio ? 0.45 2?2 1.5 v 1.425 1.5 1.575 ?0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2?2 1.2 v 1.14 1.2 1.26 ?0.3 0.35 * v ccio 0.65 * v ccio v ccio + 0.3 0.25 * v ccio 0.75 * v ccio 2?2 table 2?15. single-ended sstl, hstl, and hsul i/o reference voltage specifications for stratix v devices? preliminary (part 1 of 2) i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio v ref ? 0.04 v ref v ref + 0.04 sstl-18 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 v ref ? 0.04 v ref v ref + 0.04 sstl-15 class i, ii 1.425 1.5 1.575 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio 0.49 * v ccio 0.5 * vccio 0.51 * v ccio sstl-135 class i, ii 1.283 1.35 1.418 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio sstl-125 class i, ii 1.19 1.25 1.26 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio 0.49 * v ccio 0.5 * vccio 0.51 * v ccio sstl-12 class i, ii 1.14 1.20 1.26 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio 0.49 * v ccio 0.5 * vccio 0.51 * v ccio hstl-18 class i, ii 1.71 1.8 1.89 0.85 0.9 0.95 ? v ccio /2 ? hstl-15 class i, ii 1.425 1.5 1.575 0.68 0.75 0.9 ? v ccio /2 ?
chapter 2: dc and switching characteristics for stratix v devices 2?12 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet hstl-12 class i, ii 1.14 1.2 1.26 0.47 * v ccio 0.5 * v ccio 0.53 * v ccio ?v ccio /2 ? hsul-12 1.14 1.2 1.3 0.49 * v ccio 0.5 * v ccio 0.51 * v ccio ?? ? table 2?15. single-ended sstl, hstl, and hsul i/o reference voltage specifications for stratix v devices? preliminary (part 2 of 2) i/o standard v ccio (v) v ref (v) v tt (v) min typ max min typ max min typ max table 2?16. single-ended sstl, hstl, and hsul i/o standards signal specifications for stratix v devices?preliminary (part 1 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min sstl-2 class i ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.608 v tt + 0.608 8.1 ?8.1 sstl-2 class ii ?0.3 v ref ? 0.15 v ref + 0.15 v ccio + 0.3 v ref ? 0.31 v ref + 0.31 v tt ? 0.81 v tt + 0.81 16.2 ?16.2 sstl-18 class i ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 v tt ? 0.603 v tt + 0.603 6.7 ?6.7 sstl-18 class ii ?0.3 v ref ? 0.125 v ref + 0.125 v ccio + 0.3 v ref ? 0.25 v ref + 0.25 0.28 v ccio ? 0.28 13.4 ?13.4 sstl-15 class i ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 8?8 sstl-15 class ii ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.175 v ref + 0.175 0.2 * v ccio 0.8 * v ccio 16 ?16 sstl-135 class i, ii ? v ref ? 0.09 v ref + 0.09 ? v ref ? 0.16 v ref + 0.16 tbd (1) tbd (1) tbd (1) tbd (1) sstl-125 class i, ii ? v ref ? 0.85 v ref + 0.85 ? v ref ? 0.15 v ref + 0.15 tbd (1) tbd (1) tbd (1) tbd (1) sstl-12 class i, ii ? v ref ? 0.1 v ref + 0.1 ? v ref ? 0.15 v ref + 0.15 tbd (1) tbd (1) tbd (1) tbd (1) hstl-18 class i ? v ref ? 0.1 v ref + 0.1 ?v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8?8 hstl-18 class ii ? v ref ? 0.1 v ref + 0.1 ?v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-15 class i ? v ref ? 0.1 v ref + 0.1 ?v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 8?8 hstl-15 class ii ? v ref ? 0.1 v ref + 0.1 ?v ref ? 0.2 v ref + 0.2 0.4 v ccio ? 0.4 16 ?16 hstl-12 class i ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 8?8 hstl-12 class ii ?0.15 v ref ? 0.08 v ref + 0.08 v ccio + 0.15 v ref ? 0.15 v ref + 0.15 0.25* v ccio 0.75* v ccio 16 ?16
chapter 2: dc and switching characteristics for stratix v devices 2?13 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet hsul-12 ? v ref ? 0.13 v ref + 0.13 ? v ref ? 0.22 v ref + 0.22 0.1* v ccio 0.9* v ccio tbd (1) tbd (1) note to table 2?16 : (1) pending silicon characterization. table 2?16. single-ended sstl, hstl, and hsul i/o standards signal specifications for stratix v devices?preliminary (part 2 of 2) i/o standard v il(dc) (v) v ih(dc) (v) v il(ac) (v) v ih(ac) (v) v ol (v) v oh (v) i ol (ma) i oh (ma) min max min max max min max min table 2?17. differential sstl i/o standards for stratix v devices?preliminary i/o standard v ccio (v) v swing(dc) (v) v x(ac) (v) v swing(ac) (v) v ox(ac) (v) min typ max min max min typ max min max min typ max sstl-2 class i, ii 2.375 2.5 2.625 0.3 v ccio + 0.6 v ccio /2 ? 0.2 ? v ccio /2 + 0.2 0.62 v ccio + 0.6 v ccio /2 ? 0.15 ? v ccio /2 + 0.15 sstl-18 class i, ii 1.71 1.8 1.89 0.25 v ccio + 0.6 v ccio /2 ? 0.175 ? v ccio /2 + 0.175 0.5 v ccio + 0.6 v ccio /2 ? 0.125 ? v ccio /2 + 0.125 sstl-15 class i, ii 1.425 1.5 1.575 0.2 ? v ccio /2 ? 0.15 ? v ccio /2 + 0.15 0.35 ? ? v ccio /2 ? sstl-135 class i, ii 1.283 1.35 1.45 0.2 ? v ref ?0.135 v ccio /2 v ref + 0.135 tbd (1) tbd (1) v ref ?0.15 ? v ref +0.15 sstl-125 class i, ii 1.19 1.25 1.31 tbd (1) ? tbd (1) v ccio /2 tbd (1) tbd (1) ? tbd (1) tbd (1) tbd (1) sstl-12 class i, ii 1.14 1.2 1.26 tbd (1) ? v ref ?0.15 v ccio /2 v ref + 0.15 ?0.30 0.30 tbd (1) tbd (1) tbd (1) note to table 2?17 : (1) pending silicon characterization. table 2?18. differential hstl and hsul i/o standards for stratix v devices?preliminary i/o standard v ccio (v) v dif(dc) (v) v x(ac) (v) v cm(dc) (v) v dif(ac) (v) min typ max min max min typ max min typ max min max hstl-18 class i, ii 1.71 1.8 1.89 0.2 ? 0.78 ? 1.12 0.78 ? 1.12 0.4 ? hstl-15 class i, ii 1.425 1.5 1.575 0.2 ? 0.68 ? 0.9 0.68 ? 0.9 0.4 ? hstl-12 class i, ii 1.14 1.2 1.26 0.16 v ccio + 0.3 ? 0.5* v ccio ? 0.4* v ccio 0.5* v ccio 0.6* v ccio 0.3 v ccio + 0.48 hsul-12 1.14 1.2 1.3 0.26 0.26 0.5*v ccio ? 0.12 0.5* v ccio 0.5*v ccio + 0.12 0.4* v ccio 0.5* v ccio 0.6* v ccio 0.44 0.44
chapter 2: dc and switching characteristics for stratix v devices 2?14 electrical characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet power consumption altera offers two ways to estimate power consumption for a design?the excel-based early power estimator and the quartus ? ii powerplay power analyzer feature. 1 you typically use the interactive excel-based early power estimator before designing the fpga to get a magnitude estimate of the device power. the quartus ii powerplay power analyzer provides better quality esti mates based on the specifics of the design after you complete place-and-route. the powerplay power analyzer can apply a combination of user-entered, simulation-deriv ed, and estimated signal activities that, when combined with detailed circuit models , yields very accura te power estimates. f for more information about power estimation tools, refer to the powerplay early power estimator user guide and the powerplay power analysis chapter in the quartus ii handbook. table 2?19. differential i/o standard specifications for stratix v devices?preliminary (1) i/o standard v ccio (v) (7) v id (mv) v icm(dc) (v) v od (v) (2) v ocm (v) (2) min typ max min condition max min condition max min typ max min typ max pcml transmitter, receiver, and input reference clock pins of the high-speed transceivers use the pcml i/o standard. for transmitter, receiver, and reference clock i/o pin specifications, refer to table 2?20 on page 2?15 . 2.5 v lvds 2.375 2.5 2.625 100 v cm = 1.25 v (5) ? 0.05 d max ? 700 mbps 1.8 0.247 ? 0.6 1.125 1.25 1.375 ? 1.05 d max > 700 mbps 1.55 0.247 ? 0.6 1.125 1.25 1.375 blvds (3) 2.375 2.5 2.625 100 ? ? ? ? ? ? ? ? ? ? ? rsds (hio) 2.375 2.5 2.625 100 v cm = 1.25 v (5) ? 0.3 ? 1.4 0.1 0.2 0.6 0.5 1.2 1.4 mini- lvds (hio) 2.375 2.5 2.625 200 ? 600 0.4 ? 1.325 0.25 ? 0.6 1 1.2 1.4 lvpecl (6) 2.375 2.5 2.625 300 ? ? 0.6 d max ? 700 mbps 1.8 (4) ?????? 2.375 2.5 2.625 300 ? ? 1 d max > 700 mbps 1.6 (4) ?????? notes to table 2?19 : (1) the 1.4-v and 1.5-v pcml transceiver i/o standard specificatio ns are described in ?transceiver performance specifications? on page 2?15 . (2) rl range: 90 ? rl ? 110 ? . (3) there are no fixed v icm , v od , and v ocm specifications for blvds. they depend on the system topology. (4) for d max > 700 mbps, the minimum input voltage is 0.85 v; the maximum input voltage is 1.75 v. for f max ? 700 mbps, the minimu m input voltage is 0.45 v; the maximum input voltage is 1.95 v. (5) the minimum vid value is applicable over the entire common mode range, vcm. (6) lvpecl is only supported on dedicated clock input pins. (7) differential inputs are powered by vccpd which requires 2.5 v.
chapter 2: dc and switching characteristics for stratix v devices 2?15 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet switching characteristics this section provides performance characteri stics of the stratix v core and periphery blocks. these characteristics can be design ated as preliminary or final. transceiver performance specifications this section describes transceiver performance specifications. table 2?20 lists the stratix v gx and gs transceiver specifications. table 2?20. transceiver specifications for stratix v gx and gs devices?preliminary (1) (part 1 of 4) symbol/ description conditions ?1 commercial speed grade ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max min typ max reference clock supported i/o standards 1.2-v pcml, 1.4-v pcml, 1.5- v pcml, 2.5-v pcml, differential lvpecl, lvds, and hcsl input frequency from refclk input pins ? 40 ? 710 40 ? 710 40 ? 710 mhz duty cycle ? 45 ? 55 45 ? 55 45 ? 55 % spread-spectrum modulating clock frequency pci express ? (pcie ? ) 30 ? 33 30 ? 33 30 ? 33 khz spread-spectrum downspread pcie ? 0 to ?0.5% ?? 0 to ?0.5% ?? 0 to ?0.5% ?? on-chip termination resistors ? ? 100 ? ? 100 ? ? 100 ? ? v icm (ac coupled) ? 1000/850 (2) 1000/850 (2) 1000/850 (2) mv v icm (dc coupled) hcsl i/o standard for pcie reference clock 250 ? 550 250 ? 550 250 ? 550 mv
chapter 2: dc and switching characteristics for stratix v devices 2?16 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet transmitter refclk phase noise 10 hz ? ? -50 ? ? -50 ? ? -50 dbc/hz 100 hz ? ? -80 ? ? -80 ? ? -80 dbc/hz 1 khz ? ? -110 ? ? -110 ? ? -110 dbc/hz 10 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz 100 khz ? ? -120 ? ? -120 ? ? -120 dbc/hz 1 mhz ? ? -130 ? ? -130 ? ? -130 dbc/hz transmitter refclk phase jitter (rms) 10 khz to 20 mhz ?? 3 ?? 3 ?? 3 ps r ref ?? 2000 1% ?? 2000 1% ?? 2000 1% ? : transceiver clocks fixedclk clock frequency pcie receiver detect ? 125 ? ? 125 ? ? 125 ? mhz avalon-mm phy management clock ( phy_mgmt_clk ) frequency < 150 mhz reconfiguration clock ( mgmt_clk_clk ) frequency ? 100 ? 125 100 ? 125 100 ? 125 mhz receiver supported i/o standards 1.4-v pcml, 1.5-v pcml, 2.5-v pcml, lvpecl, and lvds data rate (standard pcs) (7) ? 600 ? 8500 600 ? 8500 600 ? 6500 mbps data rate (10g pcs) (7) ? 600 ? 14100 600 ? 12500 600 ? 8500 mbps absolute v max for a receiver pin (3) ? ? ? 1.2 ? ? 1.2 ? ? 1.2 v absolute v min for a receiver pin ? ?0.4 ? ? ?0.4 ? ? ?0.4 ? ? v maximum peak-to-peak differential input voltage v id (diff p-p) before device configuration ? ? ? 1.6 ? ? 1.6 ? ? 1.6 v maximum peak-to-peak differential input voltage v id (diff p-p) after device configuration v ccr_gxb = 1.0 v ? ? 1.8 ? ? 0.8 ? ? 1.8 v v ccr_gxb = 0.85 v ?? 2.4 ?? 2.4 ?? 2.4 v minimum differential eye opening at receiver serial input pins (4) ?85??85??85??mv table 2?20. transceiver specifications for stratix v gx and gs devices?preliminary (1) (part 2 of 4) symbol/ description conditions ?1 commercial speed grade ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max min typ max
chapter 2: dc and switching characteristics for stratix v devices 2?17 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet differential on-chip termination resistors 85?? setting 85 85 85 ? 100 ?? setting 100 100 100 ? 120 ?? setting 120 120 120 ? 150- ? setting 150 150 150 ? programmable equalization (ac gain) full bandwidth (6.25 ghz) half bandwidth (3.125 ghz) ? ? 16 ? ? 16 ? ? 16 db programmable dc gain dc gain setting = 0 ?0 ??0 ??0 ? db dc gain setting = 1 ?2 ??2 ??2 ? db dc gain setting = 2 ?4 ??4 ??4 ? db dc gain setting = 3 ?6 ??6 ??6 ? db dc gain setting = 4 ?8 ??8 ??8 ? db transmitter supported i/o standards 1.4-v and 1.5-v pcml data rate (standard pcs) ? 600 ? 8500 600 ? 8500 600 ? 6500 mbps data rate (10g pcs) ? 600 ? 14100 600 ? 12500 600 ? 8500 mbps v ocm 0.65-v setting ? 650 ? ? 650 ? ? 650 ? mv differential on-chip termination resistors 85- ? setting 85 85 85 ? 100- ? setting 100 100 100 ? 120- ? setting 120 120 120 ? 150- ? setting 150 150 150 ? rise time (5) ? 30 ? 160 30 ? 160 30 ? 160 ps fall time (5) ? 30 ? 160 30 ? 160 30 ? 160 ps cmu pll supported data range ? 600 ? 14100 600 ? 12500 600 ? 8500 mbps atx pll table 2?20. transceiver specifications for stratix v gx and gs devices?preliminary (1) (part 3 of 4) symbol/ description conditions ?1 commercial speed grade ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max min typ max
chapter 2: dc and switching characteristics for stratix v devices 2?18 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 2?21 lists the stratix v gt transceivers specifications. 1 stratix v gt devices contain both gx and gt channels. all transceiver specifications for the gx channels not listed in table 2?21 are the same as those listed in table 2?20 . supported data range vco post-divider l=1 8000 ? 14100 8000 ? 12500 8000 ? 8500 mbps l=2 4000 ? 7050 4000 ? 7050 4000 ? 7050 mbps l=4 2000 ? 3525 2000 ? 3525 2000 ? 3525 mbps l=8 1000 ? 1762.5 1000 ? 1762.5 1000 ? 1762.5 mbps input reference clock frequency (6) ? 100 ? 710 100 ? 710 100 ? 710 mhz transceiver-fpga fabric interface interface speed ? 25 ? 283 25 ? 266 25 ? 250 mhz notes to table 2?20 : (1) speed grades shown in table 2?20 refer to the pma speed grade in the device ordering code. the maximum data rate could be restricted by the core/pcs speed grade. contact your altera sales representative for the maximum data rate specifications in each speed gr ade combination offered. for more information about device ordering codes, refer to the stratix v device family overview chapter. (2) the reference clock common mo de voltage is equal to the v ccr_gxb power supply level. (3) the device cannot tolerate prolonged operation at this absolute maximum. (4) the differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. if you enable receiver equalization , the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (5) the quartus ii software automa tically selects the approp riate slew rate depending on the configured data rate or functional mode. (6) the input reference clock freque ncy options depend on the data rate and the device speed grade. (7) the line datarate may be limited by pcs-fpga interface speed grade. table 2?20. transceiver specifications for stratix v gx and gs devices?preliminary (1) (part 4 of 4) symbol/ description conditions ?1 commercial speed grade ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max min typ max table 2?21. transceiver specifications for stratix v gt devices?preliminary (part 1 of 2) symbol/ description conditions ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max reference clock v icm (ac coupled) ? 1000 1000 mv receiver data rate (standard pcs) gx channels 600 ? 8500 600 ? 8500 mbps data rate (10g pcs) gx channels 600 ? 12,500 600 ? 12,500 mbps data rate gt channels 19,600 ? 28,050 19,600 ? 25,780 mbps programmable equalization (ac gain) gt channels ? 15 ? ? 15 ? db
chapter 2: dc and switching characteristics for stratix v devices 2?19 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet differential on-chip termination resistors gt channels ? 100 ? ? 100 ? ? data rate (standard pcs) gx channels 600 ? 8500 600 ? 8500 mbps data rate (10g pcs) gx channels 600 ? 12,500 600 ? 12,500 mbps data rate gt channels 19,600 ? 28,050 19,600 ? 25,780 mbps differential on-chip termination resistors gt channels ? 100 ? ? 100 ? ? rise/fall time gt channels ? 15 ? ? 15 ? ps table 2?21. transceiver specifications for stratix v gt devices?preliminary (part 2 of 2) symbol/ description conditions ?2 commercial/industrial speed grade ?3 commercial/industrial speed grade unit min typ max min typ max
chapter 2: dc and switching characteristics for stratix v devices 2?20 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 2?22 shows the v od settings for the gx channel. table 2?22. typical v od setting for gx channel, tx termination = 100 ? ?preliminary symbol v od setting v od value (mv) v od setting v od value (mv) v od differential peak to peak typical 0 0 32 640 1 20 33 660 2 40 34 680 3 60 35 700 4 80 36 720 5 100 37 740 6 120 38 760 7 140 39 780 8 160 40 800 9 180 41 820 10 200 42 840 11 220 43 860 12 240 44 880 13 260 45 900 14 280 46 920 15 300 47 940 16 320 48 960 17 340 49 980 18 360 50 1000 19 380 51 1020 20 400 52 1040 21 420 53 1060 22 440 54 1080 23 460 55 1100 24 480 56 1120 25 500 57 1140 26 520 58 1160 27 540 59 1180 28 560 60 1200 29 580 61 1220 30 600 62 1240 31 620 63 1260
chapter 2: dc and switching characteristics for stratix v devices 2?21 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet table 2?23 shows the v od settings for the gt channel. core performance specifications this section describes the clock tree, phase-locked loop (pll), digital signal processing (dsp), memory blocks, configuration, and jtag specifications. clock tree specifications table 2?24 lists the clock tree specifications for stratix v devices. pll specifications table 2?25 lists the stratix v pll specifications when operating in both the commercial junction temperature range (0 to 85c) and the in dustrial junction temperature range (?40 to 100c). table 2?23. typical v od setting for gt channel, tx termination = 100 ? ?preliminary symbol v od setting v od value (mv) v od differential peak to peak typical 00 1200 2400 3600 4800 5 1000 table 2?24. clock tree performance for stratix v devices?preliminary (1) performance unit symbol ?2 speed grade ?3 speed grade ?4 speed grade global and regional clock 717 700 500 mhz periphery clock 550 500 500 mhz note to table 2?24 : (1) the stratix v es devices ar e limited for the 600 mhz co re clock network frequency. table 2?25. pll specifications for stratix v devices?preliminary (1) (part 1 of 3) symbol parameter min typ max unit f in input clock frequency (?2 speed grade) 5 ? 800 (2) mhz input clock frequency (?3 speed grade) 5 ? 700 (2) mhz input clock frequency (?4 speed grade) 5 ? 650 (2) mhz f inpfd input frequency to the pfd 5 ? 325 mhz f finpfd fractional input clock frequency to the pfd 50 ? 133 mhz f vco pll vco operating range (?2 speed grade) 600 ? 1600 mhz pll vco operating range (?3 speed grade) 600 ? 1400 mhz pll vco operating range (?4 speed grade) 600 ? 1300 mhz t einduty input clock or external feedback clock input duty cycle 40 ? 60 %
chapter 2: dc and switching characteristics for stratix v devices 2?22 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet f out output frequency for an internal global or regional clock (?2 speed grade) ? ? 717 (3) mhz output frequency for an internal global or regional clock (?3 speed grade) ? ? 700 (3) mhz output frequency for an internal global or regional clock (?4 speed grade) ? ? 500 (3) mhz f out_ext output frequency for an external clock output (?2 speed grade) ? ? 800 (3) mhz output frequency for an external clock output (?3 speed grade) ? ? 667 (3) mhz output frequency for an external clock output (?4 speed grade) ? ? 533 (3) mhz t outduty duty cycle for an external clock output (when set to 50% )45 50 55 % t fcomp external feedback clock compensation time ? ? 10 ns t configphase time required to reconfigure phase shift ? tbd (1) ?? f dyconfigclk dynamic configuration clock ? ? 100 mhz t lock time required to lock from the end-of-device configuration or deassertion of areset ?? 1 ms t dlock time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) ?? 1 ms f clbw pll closed-loop low bandwidth ? 0.3 ? mhz pll closed-loop medium bandwidth ? 1.5 ? mhz pll closed-loop high bandwidth (8) ?4 ? mhz t pll_pserr accuracy of pll phase shift ? ? 50 ps t areset minimum pulse width on the areset signal 10 ? ? ns t inccj (4) , (5) input clock cycle-to-cycle jitter (f ref 100 mhz) ? ? 0.15 ui (p-p) input clock cycle-to-cycle jitter (f ref < 100 mhz) ?750 ? +750 ps (p-p) t outpj_dc (6) period jitter for dedicated clock output (f out 100 mhz) ? ? tbd (1) ps (p-p) period jitter for dedicated clock output (f out < 100 mhz) ? ? tbd (1) mui (p-p) t outccj_dc (6) cycle-to-cycle jitter for a dedicated clock output (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for a dedicated clock output (f out <100mhz) ??tbd (1) mui (p-p) t outpj_io (6) , (9) period jitter for a clock output on a regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for a clock output on a regular i/o (f out <100mhz) ??tbd (1) mui (p-p) t outccj_io (6) , (9) cycle-to-cycle jitter for a clock output on a regular i/o (f out 100 mhz) ??tbd (1) ps (p-p) cycle-to-cycle jitter for a clock output on a regular i/o (f out <100mhz) ??tbd (1) mui (p-p) table 2?25. pll specifications for stratix v devices?preliminary (1) (part 2 of 3) symbol parameter min typ max unit
chapter 2: dc and switching characteristics for stratix v devices 2?23 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet dsp block specifications table 2?26 lists the stratix v dsp block performance specifications. t casc_outpj_dc (6) , (7) period jitter for a dedicated clock output in cascaded plls (f out 100 mhz) ??tbd (1) ps (p-p) period jitter for a dedicated clock output in cascaded plls (f out < 100 mhz) ??tbd (1) mui (p-p) f drift frequency drift after pfdena is disabled for a duration of 100 s ? ? 10 % dk bit bit number of delta sigma modulator (dsm) ? 24 ? bits k value numerator of fraction ? 8388608 ? ? f res resolution of vco frequency (f inpfd = 100 mhz) ? 5.96 ? hz notes to table 2?25 : (1) pending silicon characterization. (2) this specification is limited in the qu artus ii software by the i/o m aximum frequency. the maximu m i/o frequency is differen t for each i/o standard. (3) this specification is limited by the lower of the two: i/o f max or f out of the pll. (4) a high input jitter directly affects th e pll output jitter. to have low pll output clock jitter, you must provide a clean cl ock source < 120 ps. (5) f ref is fin/n when n = 1. (6) peak-to-peak jitter with a probability level of 10 ?12 (14 sigma, 99.99999999974404% confidence level). the output jitter specification applies to the intrinsic jitter of the pl l, when an input jitter of 30 ps is applied. the external memory interface clock output jitter specifications use a different measurement method and are available in table 2?38 on page 2?33 . (7) the cascaded pll specification is only applicable with the following condition: a. upstream pll: 0.59mhz d upstream pll bw < 1 mhz b. downstream pll: downstream pll bw > 2 mhz (8) high bandwidth pll settings are not supported in external feedback mode. (9) the external memory interface clock outpu t jitter specifications use a different m easurement method, which is available in table 2?36 on page 2?32 . table 2?25. pll specifications for stratix v devices?preliminary (1) (part 3 of 3) symbol parameter min typ max unit table 2?26. block performance specifications for stratix v dsp devices?preliminary (1) (part 1 of 2) mode performance unit ?1 speed grade ?2 speed grade ?3 speed grade ?4 speed grade modes using one dsp three 9 9 690 620 500 440 mhz one 18 18 690 620 500 440 mhz two partial 18 18 (or 16 16) 690 620 500 440 mhz one 27 27 520 470 370 330 mhz one 36 18 520 470 370 330 mhz one sum of two 18 18 (one sum of two 16 16) 570 520 410 360 mhz one sum of square 520 470 370 330 mhz one 18 18 plus 36 (a b) + c 570 520 410 360 mhz modes using two dsps
chapter 2: dc and switching characteristics for stratix v devices 2?24 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet memory block specifications table 2?27 lists the stratix v memory block specifications. three 18 18 570 520 410 360 mhz one sum of four 18 18 490 440 350 310 mhz one sum of two 27 27 490 440 350 310 mhz one sum of two 36 18 490 440 350 310 mhz one complex 18 18 570 520 410 360 mhz one 36 36 460 410 330 290 mhz modes using three dsps one complex 18 25 400 360 290 250 mhz modes using four dsps one complex 27 27 490 440 350 310 mhz note to table 2?26 : (1) these numbers are preliminary pending silicon characterization. table 2?26. block performance specifications for stratix v dsp devices?preliminary (1) (part 2 of 2) mode performance unit ?1 speed grade ?2 speed grade ?3 speed grade ?4 speed grade table 2?27. memory block performance specifications for stratix v devices?preliminary (1) , (2) , (3) (part 1 of 2) memory mode resources used performance unit aluts memory c1 speed grade c2 speed grade c3 speed grade i3 speed grade c4 speed grade i4 speed grade mlab single port, all supported widths 0 1 ? 600 500 500 450 450 mhz simple dual-port, x32/x64 width 0 1 ? 450 400 tbd 315 tbd mhz simple dual-port, x16 width 0 1 ? 675 533 533 400 400 mhz rom, all supported widths 0 1 ? 600 500 500 450 450 mhz
chapter 2: dc and switching characteristics for stratix v devices 2?25 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet jtag configuration specifications table 2?28 lists the jtag timing parameters and values for stratix v devices. m20k block single-port, all supported widths 0 1 800 730 680 520 570 470 mhz simple dual-port, all supported widths 0 1 800 730 680 520 570 470 mhz simple dual-port with the read-during-write option set to old data , all supported widths 0 1 600 550 470 470 410 410 mhz simple dual-port with ecc enabled, 512 32 0 1 520 470 410 410 360 360 mhz simple dual-port with ecc and optional pipeline registers enabled, 512 32 0 1 690 620 520 520 470 470 mhz true dual port, all supported widths 0 1 800 730 680 520 570 470 mhz rom, all supported widths 0 1 800 730 680 520 570 470 mhz min pulse width (clock high time) ? ? 800 780 830 830 890 890 ps min pulse width (clock low time) ? ? 570 520 650 650 720 720 ps notes to table 2?27 : (1) these numbers are preliminary pending silicon characterization. (2) to achieve the maximum memory block perfor mance, use a memory block cl ock that comes through global clock routing from an on -chip pll set to 50% output duty cycle. use the quartus ii software to report timing for this a nd other memory block clocking schemes. (3) when you use the error detection cyclical redundancy check (crc) featur e, there is no degradation in f max . table 2?27. memory block performance specifications for stratix v devices?preliminary (1) , (2) , (3) (part 2 of 2) memory mode resources used performance unit aluts memory c1 speed grade c2 speed grade c3 speed grade i3 speed grade c4 speed grade i4 speed grade table 2?28. jtag timing parameters and values for stratix v devices?preliminary (1) symbol description min max unit t jcp tck clock period 30 ? ns t jch tck clock high time 14 ? ns t jcl tck clock low time 14 ? ns t jpsu (tdi) tdi jtag port setup time 2 ? ns t jpsu (tms) tms jtag port setup time 3 ? ns t jph jtag port hold time 5 ? ns t jpco jtag port clock to output ? 11 (2) ns t jpzx jtag port high impedance to valid output ? 14 (2) ns t jpxz jtag port valid output to high impedance ? 14 (2) ns notes to table 2?28 : (1) these numbers are preliminary pending silicon characterization. (2) a 1 ns adder is required for each v ccio voltage step down from 3.0 v. for example, t jpco = 12 ns if v ccio of the tdo i/o bank = 2.5 v, or 13 ns if it equals 1.8 v.
chapter 2: dc and switching characteristics for stratix v devices 2?26 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet temperature sensing diode specifications table 2?29 lists the specifications for the stratix v temperature sensing diode. periphery performance this section describes periphery performanc e, including high-speed i/o and external memory interface. i/o performance supports several system interfaces, such as the lvds high-speed i/o interface, external memory interface, and the pci/pci-x bus interface. general-purpose i/o standards such as 3.3-, 2.5- , 1.8-, and 1.5- lvttl/lvcmos are capable of a typical 167 mhz and 1.2- lvcmos at 100 mhz interfacing frequency with a 10 pf load. 1 the actual achievable frequency depends on design- and system-specific factors. you must perform hspice/ibis simulations base d on your specific design and system setup to determine the maximum achievable frequency in your system. high-speed i/o specification table 2?30 lists high-speed i/o timing for stratix v devices. table 2?29. external temperature sensing diode specifications for stratix v devices? preliminary description min typ max unit i bias , diode source current 8 ? 200 ?a v bias, voltage across diode 0.3 ? 0.9 v series resistance ? ? < 1 ? diode ideality factor ? ? 1.01 ? table 2?30. high-speed i/o specifications for stratix v devices?preliminary (1), (2) (part 1 of 3) symbol conditions ?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max f hsclk_in (input clock frequency) true differential i/o standards clock boost factor w = 1 to 40 (4) 5 ? 717 5 ? 625 5 ? 525 mhz f hsclk_in (input clock frequency) single ended i/o standards (3) clock boost factor w = 1 to 40 (4) 5 ? 717 5 ? 625 5 ? 525 mhz f hsclk_in (input clock frequency) single ended i/o standards clock boost factor w = 1 to 40 (4) 5 ? 520 5 ? 420 5 ? 420 mhz f hsclk_out (output clock frequency) ?5? 717 (5) 5? 625 (5) 5? 525 (5) mhz
chapter 2: dc and switching characteristics for stratix v devices 2?27 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet transmitter true differential i/o standards - f hsdr (data rate) serdes factor j = 3 to 10 (9) (6) ? 1434 (6) ?1250 (6) ? 1050 mbps serdes factor j = 2, uses ddr registers (6) ? (7) (6) ? (7) (6) ? (7) mbps serdes factor j = 1, uses sdr register (6) ? (7) (6) ? (7) (6) ? (7) mbps emulated differential i/o standards with three external output resistor networks - f hsdr (data rate) (10) serdes factor j = 4 to 10 (6) ? 1100 (6) ? 840 (6) ? 840 mbps t x jitter - true differential i/o standards total jitter for data rate 600 mbps - 1.25 gbps ? ? 160 ? ? 160 ? ? 160 ps total jitter for data rate < 600 mbps ? ? 0.1 ? ? 0.1 ? ? 0.1 ui t x jitter - emulated differential i/o standards with three external output resistor network total jitter for data rate 600 mbps - 1.25 gbps ? ? 300 ? ? 300 ? ? 325 ps total jitter for data rate < 600 mbps ?? 0.2 ?? 0.2 ??0.25 ui t duty transmitter output clock duty cycle for both true and emulated differential i/o standards 45 50 55 45 50 55 45 50 55 % t rise & t fall true differential i/o standards ? ? 160 ? ? 200 ? ? 200 ps emulated differential i/o standards with three external output resistor networks ? ? 250 ? ? 250 ? ? 300 ps tccs true differential i/o standards ? ? 150 ? ? 150 ? ? 150 ps emulated differential i/o standards ? ? 300 ? ? 300 ? ? 300 ps receiver true differential i/o standards - f hsdrdpa (data rate) serdes factor j = 3 to 10 150 ? 1434 150 ? 1250 150 ? 1050 mbps f hsdr (data rate) serdes factor j = 3 to 10 (6) ? (8) (6) ? (8) (6) ? (8) mbps serdes factor j = 2, uses ddr registers (6) ? (7) (6) ? (7) (6) ? (7) mbps serdes factor j = 1, uses sdr register (6) ? (7) (6) ? (7) (6) ? (7) mbps table 2?30. high-speed i/o specifications for stratix v devices?preliminary (1), (2) (part 2 of 3) symbol conditions ?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max
chapter 2: dc and switching characteristics for stratix v devices 2?28 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet figure 2?1 shows the dynamic phase alignment (d pa) lock time specifications with the dpa pll calibration option enabled. table 2?31 lists the dpa lock time specifications for stratix v gx devices. dpa mode dpa run length ? ? ? 10000 ? ? 10000 ? ? 10000 ui soft cdr mode soft-cdr ppm tolerance ? ? ? 300 ? ? 300 ? ? 300 ppm non dpa mode sampling window ? ? ? 300 ? ? 300 ? ? 300 ps notes to table 2?30 : (1) when j = 3 to 10, use the serializer/deserializer (serdes) block. (2) when j = 1 or 2, bypass the serdes block. (3) this only applies to dpa and soft-cdr modes. (4) clock boost factor (w) is the ratio between the input data rate to the input clock rate. (5) this is achieved by using the lvds clock network. (6) the minimum specification depe nds on the clock source (for example, the pll an d clock pin) and the clock routing resource (g lobal, regional, or local) that you use. the i/o differential buffer and inpu t register do not have a minimum toggle rate. (7) the maximum ideal frequency is the serdes factor (j) x the pl l maximum output frequency (fout) provided you can close the de sign timing and the signal integrity si mulation is clean. (8) you can estimate the achievable maximum data rate for non-dpa mode by perfor ming link timing closure analysis. you must cons ider the board skew margin, transmitter delay margin, and receiver sampling margin to determin e the maximum data rate supported. (9) if the receiver with dpa enabled an d transmitter are using shared plls, the minimum data rate is 150 mbps. (10) you must calculate the leftover timing margin in the receiver by performing link timing closure anal ysis. you must consider the board skew margin, transmitter channel-to-channel skew , and receiver sampling ma rgin to determine le ftover timing margin. table 2?30. high-speed i/o specifications for stratix v devices?preliminary (1), (2) (part 3 of 3) symbol conditions ?2 speed grade ?3 speed grade ?4 speed grade unit min typ max min typ max min typ max figure 2?1. dpa lock time specification with dpa pll calibration enabled rx_dpa_locked rx_reset dpa lock time 256 data transitions 96 slow clock cycles 256 data transitions 256 data transitions 96 slow clock cycles table 2?31. dpa lock time specifications for stratix v gx devices only?preliminary (part 1 of 2) (1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum spi-4 00000000001111111111 2 128 640 data transitions parallel rapid i/o 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions
chapter 2: dc and switching characteristics for stratix v devices 2?29 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions notes to table 2?31 : (1) the dpa lock time is for one channel. (2) one data transition is defined as a 0-to-1 or 1-to-0 transition. (3) the dpa lock time stated in this table appl ies to both co mmercial and in dustrial grade. (4) this is the number of repetition s for the stated training pattern to achieve the 256 data transitions. table 2?31. dpa lock time specifications for stratix v gx devices only?preliminary (part 2 of 2) (1) , (2) , (3) standard training pattern number of data transitions in one repetition of the training pattern number of repetitions per 256 data transitions (4) maximum
chapter 2: dc and switching characteristics for stratix v devices 2?30 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet figure 2?2 shows the lvds soft-clock data recovery (cdr)/dpa sinusoidal jitter tolerance specification for a data rate ? lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate ? figure 2?2. lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate ? 1.25 gbps lvds soft-cdr/dpa sinusoidal jitter tolerance specification f1 f2 f3 f4 jitter frequency (hz) jitter amphlitude (ui) 0.1 0.35 8.5 25 table 2?32. lvds soft-cdr/dpa sinusoidal jitter mask values for a data rate ? 1.25 gbps? preliminary jitter frequency (hz) sinusoidal jitter (ui) f1 10,000 25.000 f2 17,565 25.000 f3 1,493,000 0.350 f4 50,000,000 0.350
chapter 2: dc and switching characteristics for stratix v devices 2?31 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet figure 2?3 shows the lvds soft-cdr/dpa sinusoidal jitter tolerance specification for a data rate < 1.25 gbps. dll range, dqs logic block, and memo ry output clock ji tter specifications table 2?33 lists the dll range specification for stratix v devices. the dll is always in 8-tap mode in stratix v devices. table 2?34 lists the dqs phase offset delay per stage for stratix v devices. figure 2?3. lvds soft-cdr/dpa sinusoidal jitter tole rance specification for a data rate < 1.25 gbps 0.1 ui p-p baud/1667 20 mhz frequency sinusoidal jitter amplitude 20db/dec table 2?33. dll range specifications for stratix v devices (1) ?2 speed grade ?3 speed grade ?4 speed grade unit 300-1120 300-890 300-890 mhz note to table 2?33 : (1) stratix v devices support memory interface frequencies lower than 300 mhz, although the reference clock that feeds the dll must be at least 300 mhz. to support interfaces below 300 mhz, mult iply the reference clock feeding the dll to ensure the frequency is within the supported range of the dll. table 2?34. dqs phase offset delay per setting for stratix v devices?preliminary (1) , (2) , (3) speed grade min max unit ?2 7 13 ps ?3 7 15 ps ?4 7 16 ps notes to table 2?34 : (1) these numbers are preliminary pending silicon characterization. (2) the typical value equals the averag e of the minimum and maximum values. (3) the delay settings are lin ear with a cumulative delay variation of 40 ps for all speed grad es. for example, when using a ?2 speed grade and applying a 10-phase offset setting to a 90 phase shift at 400 mhz, the expected average cumulative delay is [625 ps + (10 10 ps) 20 ps] = 725 ps 20 ps.
2?32 chapter 2: dc and switching characteristics for stratix v devices switching characteristics stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet table 2?35 lists the dqs phase shift error for stratix v devices. table 2?36 lists the memory output clock jitter specifications for stratix v devices. table 2?35. dqs phase shift error specification for dll-delayed clock (t dqs_pserr ) for stratix v devices?preliminary (1) , (2) number of dqs delay buffers ?2 speed grade ?3 speed grade ?4 speed grade unit 1262830ps 2525660ps 3788490ps 4 104 112 120 ps notes to table 2?35 : (1) the numbers are preliminary pe nding silicon ch aracterization. (2) this error specificat ion is the absolute maximum and minimum error. for exam ple, skew on three dqs delay buffers in a ?2 speed gr ade is 78 ps or 39 ps. table 2?36. memory output clock jitter specification for stratix v devices (1) clock network parameter symbol ?2 speed grade ?3 speed grade ?4 speed grade unit min max min max min max regional clock period jitter t jit(per) ?50 50 ?55 55 ?55 55 ps cycle-to-cycle period jitter t jit(cc) ?100 100 ?110 110 ?110 110 ps duty cycle jitter t jit(duty) ?50 50 ?82.5 82.5 ?82.5 82.5 ps global clock period jitter t jit(per) ?75 75 ?82.5 82.5 ?82.5 82.5 ps cycle-to-cycle period jitter t jit(cc) ?150 150 ?165 165 ?165 165 ps duty cycle jitter t jit(duty) ?75 75 ?90 90 ?90 90 ps phy clock clock period jitter t jit(per) ?25 25 ?30 30 ?35 35 ps cycle-to-cycle period jitter t jit(cc) ?50 50 ?60 60 ?70 70 ps duty cycle jitter t jit(duty) ?37.5 37.5 ?45 45 ?56 56 ps note to table 2?36 : (1) the clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and ddio circuits clocked by a pll output routed on a phy, regional, or global clock networ k as specified. altera recommend s using phy clock networks whenev er possible.
chapter 2: dc and switching characteristics for stratix v devices 2?33 switching characteristics february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet oct calibration block specifications table 2?37 lists the oct calibration block specifications for stratix v devices. duty cycle distorti on (dcd) specifications table 2?38 lists the worst-case dcd for stratix v devices. table 2?37. oct calibration block specifications for stratix v devices?preliminary (1) symbol description min typ max unit octusrclk clock required by the oct calibration blocks ? ? 20 mhz t octcal number of octusrclk clock cycles required for oct r s /r t calibration ? 1000 ? cycles t octshift number of octusrclk clock cycles required for the oct code to shift out ? 32 ? cycles t rs_rt time required between the dyn_term_ctrl and oe signal transitions in a bidirectional i/o buffer to dynamically switch between oct r s and r t ( figure 2?4 ) ?2.5? ns note to table 2?37 : (1) pending silicon characterization. figure 2?4. timing diagram for oe and dyn_term_ctrl signals table 2?38. worst-case dcd on stratix v i/o pins?preliminary (1) symbol ?2 speed grade ?3 speed grade ?4 speed grade unit min max min max min max output duty cycle 45 55 45 55 45 55 % note to table 2?38 : (1) the numbers are preliminary pe nding silicon ch aracterization. oe tristate rx rx tx dyn_term_ctrl t rs_rt tristate t rs_rt
2?34 chapter 2: dc and switching characteristics for stratix v devices i/o timing stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet i/o timing altera offers two ways to determine i/o timing?the excel-based i/o timing and the quartus ii timing analyzer. excel-based i/o timing provides pin timing performance for each device density and speed grade. the data is typically used prior to designing the fpga to get an estimate of the timing budget as part of the li nk timing analysis. the quartus ii timing analyzer provides a more accurate and precise i/o timing data based on the specifics of the design after you complete place-and-route. f you can download the excel-based i/o timing spreadsheet from the stratix v devices documentation webpage. programmable ioe delay table 2?39 lists the stratix v ioe programmable delay settings. programmable output buffer delay table 2?40 lists the delay chain settings that control the rising and falling edge delays of the output buffer. the default delay is 0 ps. table 2?39. ioe programmable delay for stratix v devices?preliminary (1) parameter (2) available settings min offset (3) fast model slow model industrial commercial c2 c3 c4 i3 i4 unit d1 63 0 0.471 0.514 0.800 0.843 0.918 0.850 0.924 ns d2 31 0 0.274 0.274 0.423 0.456 0.501 0.453 0.498 ns d3 7 0 1.668 1.735 2.830 2.985 3.252 3.007 3.274 ns d5 63 0 0.493 0.474 0.835 0.882 0.960 0.888 0.966 ns d6 31 0 0.273 0.258 0.463 0.488 0.532 0.492 0.536 ns notes to table 2?39 : (1) pending the quartus ii software extraction. (2) you can set this value in th e quartus ii software by selecting d1 , d2 , d3 , d5 , and d6 in the assignment name column of assignment editor . (3) minimum offset does not include the intrinsic delay. table 2?40. programmable output buffer delay for stratix v devices?preliminary (1) , (2) symbol parameter typical unit d outbuf rising and/or falling edge delay 0 (default) ps 50 ps 100 ps 150 ps notes to table 2?40 : (1) pending the quartus ii software extraction. (2) you can set the progra mmable output buffer de lay in the quartus ii software by setting the output buffer delay control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the output buffer delay assignment.
chapter 2: dc and switching characteristics for stratix v devices 2?35 glossary february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet glossary table 2?41 lists the glossary for this chapter. table 2?41. glossary (part 1 of 4) letter subject definitions a b c ?? d differential i/o standards receiver input waveforms transmitter output waveforms e ?? f f hsclk left and right pll input clock frequency. f hsdr high-speed i/o block?maximum and minimum lvds data transfer rate (f hsdr = 1/tui), non-dpa. f hsdrdpa high-speed i/o block?maximum and minimum lvds data transfer rate (f hsdrdpa = 1/tui), dpa. g h i ?? single-ended waveform differential waveform positive channel (p) = v ih n egative channel (n) = v il ground v id v id v id p ? n = 0 v v cm single-ended waveform differential waveform positive channel (p) = v oh n egative channel (n) = v ol ground v od v od v od p ? n = 0 v v cm
2?36 chapter 2: dc and switching characteristics for stratix v devices glossary stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet j j high-speed i/o block?deserialization factor (width of parallel data bus). jtag timing specifications jtag timing specifications: k l m n o ?? p pll specifications diagram of pll specifications (1) note: (1) core clock can only be fed by dedicated clock input pins or pll outputs. q ?? rr l receiver differential input discrete resistor (external to the stratix v device). table 2?41. glossary (part 2 of 4) letter subject definitions tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms core clock external feedback reconfigurable in user mode key clk n pfd switchover delta sigma modulator vco cp lf clkout pins gclk rclk f inpfd f in f vco f out f out_ext counters c0..c17 4
chapter 2: dc and switching characteristics for stratix v devices 2?37 glossary february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet s sw (sampling window) timing diagram?the period of time during which the data must be valid in order to capture it correctly. the setup and hold times determine the ideal strobe position within the sampling window, as shown: single-ended voltage referenced i/o standard the jedec standard for sstl and hstl i/o defines both the ac and dc input signal values. the ac values indicate the voltage levels at which the receiver must meet its timing specifications. the dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. after the receiver input has crossed the ac value, the receiver changes to the new logic state. the new logic state is then maintained as long as the input stays beyond the ac threshold. this approach is intended to provide predictable receiver timing in the presence of input waveform ringing, as shown: single-ended voltage referenced i/o standard t t c high-speed receiver and transmitter input and output clock period. tccs (channel- to-channel-skew) the timing difference between the fastest and slowest output edges, including t co variation and clock skew, across channels driven by the same pll. the clock is included in the tccs measurement (refer to the timing diagram figure under sw in this table). t duty high-speed i/o block?duty cycle on the high-speed transmitter output clock. timing unit interval (tui) the timing budget allowed for skew, propagation delays, and the data sampling window. (tui = 1/(receiver input clock frequency multiplication factor) = t c /w ) t fall signal high-to-low transition time (80-20%) t inccj cycle-to-cycle jitter tolerance on the pll clock input. t outpj_io period jitter on the general purpose i/o driven by a pll. t outpj_dc period jitter on the dedicated clock output driven by a pll. t rise signal low-to-high transition time (20-80%) u ?? table 2?41. glossary (part 3 of 4) letter subject definitions bit time 0.5 x tccs rskm sampling window (sw) rskm 0.5 x tccs v ih ( ac ) v ih(dc) v ref v il(dc) v il(ac ) v oh v ol v ccio v ss
2?38 chapter 2: dc and switching characteristics for stratix v devices document revision history stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet document revision history table 2?42 lists the revision history for this chapter. v v cm(dc) dc common mode input voltage. v icm input common mode voltage?the common mode of the differential signal at the receiver. v id input differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. v dif(ac) ac differential input voltage?minimum ac input differential voltage required for switching. v dif(dc) dc differential input voltage? minimum dc input differential voltage required for switching. v ih voltage input high?the minimum positive voltage applied to the input which is accepted by the device as a logic high. v ih(ac) high-level ac input voltage v ih(dc) high-level dc input voltage v il voltage input low?the maximum positive voltage applied to the input which is accepted by the device as a logic low. v il(ac) low-level ac input voltage v il(dc) low-level dc input voltage v ocm output common mode voltage?the common mode of the differential signal at the transmitter. v od output differential voltage swing?the difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. v swing differential input voltage v x input differential cross point voltage v ox output differential cross point voltage w w high-speed i/o block?clock boost factor x y z ?? table 2?41. glossary (part 4 of 4) letter subject definitions table 2?42. document revision history (part 1 of 2) date version changes february 2012 2.3 updated table 2?20 , table 2?25 , table 2?26 , and table 2?27 . december 2011 2.2 added table 2?31. updated table 2?28 and table 2?34. november 2011 2.1 added table 2?2 and table 2?21 and updated table 2?5 with information about stratix v gt devices. updated table 2?11, table 2?13, table 2?20, and table 2?25. various edits throughout to fix sprs.
chapter 2: dc and switching characteristics for stratix v devices 2?39 document revision history february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet may 2011 2.0 updated table 2?4, table 2?18, table 2?19, table 2?21, table 2?22, table 2?23, and table 2?24. updated the ?dq logic block and memory output clock jitter specifications? title. chapter moved to volume 1. minor text edits. december 2010 1.1 updated table 1?2, table 1?4, table 1?19, and table 1?23. converted chapter to the new template. minor text edits. july 2010 1.0 initial release. table 2?42. document revision history (part 2 of 2) date version changes
2?40 chapter 2: dc and switching characteristics for stratix v devices document revision history stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet
february 2012 altera corporation stratix v device handbook volume 1: overview and datasheet additional information this chapter provides additional info rmation about the document and altera. how to contact altera to locate the most up-to-date informat ion about altera products, refer to the following table. typographic conventions the following table shows the typographic conventions this document uses. contact (1) contact method address technical support website www.altera.com/support technical training website www.altera.com/training email custrain@altera.com product literature website www.altera.com/literature nontechnical support (general) email nacomp@altera.com (software licensing) email authorization@altera.com note to table: (1) you can also contact yo ur local altera sales office or sales representative. visual cue meaning bold type with initial capital letters indicate command names, dialog box titles, dialog box options, and other gui labels. for example, save as dialog box. for gui elements, capitalization matches the gui. bold type indicates directory names, project names, di sk drive names, file names, file name extensions, software utility names, and gui labels. for example, \qdesigns directory, d: drive, and chiptrip.gdf file. italic type with initial capital letters indicate document titles. for example, stratix iv design guidelines . italic type indicates variables. for example, n + 1. variable names are enclosed in angle brackets (< >). for example, and .pof file. initial capital letters indicate keyboard keys and menu names. for example, the delete key and the options menu. ?subheading title? quotation marks indicate references to sections in a document and titles of quartus ii help topics. for example, ?typographic conventions.?
info?2 additional information typographic conventions stratix v device handbook february 2012 altera corporation volume 1: overview and datasheet courier type indicates signal, port, register, bit, block, and primitive names. for example, data1 , tdi , and input . the suffix n denotes an active-low signal. for example, resetn . indicates command line commands and anything that must be typed exactly as it appears. for example, c:\qdesigns\tutorial\chiptrip.gdf . also indicates sections of an actual file, such as a report file, references to parts of files (for example, the ahdl keyword subdesign ), and logic function names (for example, tri ). r an angled arrow instructs you to press the enter key. 1., 2., 3., and a., b., c., and so on numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. bullets indicate a list of items when the sequence of the items is not important. 1 the hand points to information that requires special attention. h the question mark directs you to a software help system with related information. f the feet direct you to another document or website with related information. ? the multimedia icon directs you to a related multimedia presentation. c a caution calls attention to a condition or possible situation that can damage or destroy the product or your work. w a warning calls attention to a condition or possible situation that can cause you injury. the envelope links to the email subscription management center page of the altera website, where you can sign up to receive update notifications for altera documents. visual cue meaning

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